[PATCH 09/21] net: Remove smc91111 ethernet driver
Ramon Fried
rfried.dev at gmail.com
Sat Aug 6 19:47:16 CEST 2022
On Tue, Aug 2, 2022 at 2:37 PM Tom Rini <trini at konsulko.com> wrote:
>
> This driver has not been converted to DM_ETH. The migration deadline
> passed 2 years ago.
>
> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: David Feng <fenghua at phytium.com.cn>
> Cc: Liviu Dudau <liviu.dudau at foss.arm.com>
> Cc: Andre Przywara <andre.przywara at arm.com>
> Signed-off-by: Tom Rini <trini at konsulko.com>
> ---
> README | 14 -
> board/armltd/integrator/integrator.c | 3 -
> board/armltd/vexpress64/vexpress64.c | 3 -
> drivers/net/Makefile | 1 -
> drivers/net/smc91111.c | 1307 -------------------------
> drivers/net/smc91111.h | 632 ------------
> examples/standalone/Makefile | 1 -
> examples/standalone/smc91111_eeprom.c | 372 -------
> include/configs/integratorcp.h | 8 -
> include/configs/vexpress_aemv8.h | 6 -
> 10 files changed, 2347 deletions(-)
> delete mode 100644 drivers/net/smc91111.c
> delete mode 100644 drivers/net/smc91111.h
> delete mode 100644 examples/standalone/smc91111_eeprom.c
>
> diff --git a/README b/README
> index a6c306149c73..98185af62463 100644
> --- a/README
> +++ b/README
> @@ -565,20 +565,6 @@ The following options need to be configured:
> CONFIG_LAN91C96_USE_32_BIT
> Define this to enable 32 bit addressing
>
> - CONFIG_SMC91111
> - Support for SMSC's LAN91C111 chip
> -
> - CONFIG_SMC91111_BASE
> - Define this to hold the physical address
> - of the device (I/O space)
> -
> - CONFIG_SMC_USE_32_BIT
> - Define this if data bus is 32 bits
> -
> - CONFIG_SMC_USE_IOFUNCS
> - Define this to use i/o functions instead of macros
> - (some hardware wont work with macros)
> -
> CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
> Define this if you have more then 3 PHYs.
>
> diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c
> index e734ceae8890..4959a7fd6dcf 100644
> --- a/board/armltd/integrator/integrator.c
> +++ b/board/armltd/integrator/integrator.c
> @@ -179,9 +179,6 @@ extern void dram_query(void);
> int board_eth_init(struct bd_info *bis)
> {
> int rc = 0;
> -#ifdef CONFIG_SMC91111
> - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
> -#endif
> return rc;
> }
> #endif
> diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
> index 709ebf3fb085..05a7a25c32ec 100644
> --- a/board/armltd/vexpress64/vexpress64.c
> +++ b/board/armltd/vexpress64/vexpress64.c
> @@ -200,9 +200,6 @@ int board_eth_init(struct bd_info *bis)
> {
> int rc = 0;
> #ifndef CONFIG_DM_ETH
> -#ifdef CONFIG_SMC91111
> - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
> -#endif
> #ifdef CONFIG_SMC911X
> rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
> #endif
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index 9536af11946f..ac9818107e7e 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -78,7 +78,6 @@ obj-$(CONFIG_RTL8139) += rtl8139.o
> obj-$(CONFIG_RTL8169) += rtl8169.o
> obj-$(CONFIG_SH_ETHER) += sh_eth.o
> obj-$(CONFIG_SJA1105) += sja1105.o
> -obj-$(CONFIG_SMC91111) += smc91111.o
> obj-$(CONFIG_SMC911X) += smc911x.o
> obj-$(CONFIG_SNI_AVE) += sni_ave.o
> obj-$(CONFIG_SNI_NETSEC) += sni_netsec.o
> diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c
> deleted file mode 100644
> index 61d7f3df69ee..000000000000
> --- a/drivers/net/smc91111.c
> +++ /dev/null
> @@ -1,1307 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*------------------------------------------------------------------------
> - . smc91111.c
> - . This is a driver for SMSC's 91C111 single-chip Ethernet device.
> - .
> - . (C) Copyright 2002
> - . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> - . Rolf Offermanns <rof at sysgo.de>
> - .
> - . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
> - . Developed by Simple Network Magic Corporation (SNMC)
> - . Copyright (C) 1996 by Erik Stahlman (ES)
> - .
> - .
> - . Information contained in this file was obtained from the LAN91C111
> - . manual from SMC. To get a copy, if you really want one, you can find
> - . information under www.smsc.com.
> - .
> - .
> - . "Features" of the SMC chip:
> - . Integrated PHY/MAC for 10/100BaseT Operation
> - . Supports internal and external MII
> - . Integrated 8K packet memory
> - . EEPROM interface for configuration
> - .
> - . Arguments:
> - . io = for the base address
> - . irq = for the IRQ
> - .
> - . author:
> - . Erik Stahlman ( erik at vt.edu )
> - . Daris A Nevil ( dnevil at snmc.com )
> - .
> - .
> - . Hardware multicast code from Peter Cammaert ( pc at denkart.be )
> - .
> - . Sources:
> - . o SMSC LAN91C111 databook (www.smsc.com)
> - . o smc9194.c by Erik Stahlman
> - . o skeleton.c by Donald Becker ( becker at cesdis.gsfc.nasa.gov )
> - .
> - . History:
> - . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
> - . 10/17/01 Marco Hasewinkel Modify for DNP/1110
> - . 07/25/01 Woojung Huh Modify for ADS Bitsy
> - . 04/25/01 Daris A Nevil Initial public release through SMSC
> - . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
> - ----------------------------------------------------------------------------*/
> -
> -#include <common.h>
> -#include <command.h>
> -#include <config.h>
> -#include <malloc.h>
> -#include <linux/delay.h>
> -#include "smc91111.h"
> -#include <net.h>
> -
> -/* Use power-down feature of the chip */
> -#define POWER_DOWN 0
> -
> -#define NO_AUTOPROBE
> -
> -#define SMC_DEBUG 0
> -
> -#if SMC_DEBUG > 1
> -static const char version[] =
> - "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil at snmc.com)\n";
> -#endif
> -
> -/* Autonegotiation timeout in seconds */
> -#ifndef CONFIG_SMC_AUTONEG_TIMEOUT
> -#define CONFIG_SMC_AUTONEG_TIMEOUT 10
> -#endif
> -
> -/*------------------------------------------------------------------------
> - .
> - . Configuration options, for the experienced user to change.
> - .
> - -------------------------------------------------------------------------*/
> -
> -/*
> - . Wait time for memory to be free. This probably shouldn't be
> - . tuned that much, as waiting for this means nothing else happens
> - . in the system
> -*/
> -#define MEMORY_WAIT_TIME 16
> -
> -
> -#if (SMC_DEBUG > 2 )
> -#define PRINTK3(args...) printf(args)
> -#else
> -#define PRINTK3(args...)
> -#endif
> -
> -#if SMC_DEBUG > 1
> -#define PRINTK2(args...) printf(args)
> -#else
> -#define PRINTK2(args...)
> -#endif
> -
> -#ifdef SMC_DEBUG
> -#define PRINTK(args...) printf(args)
> -#else
> -#define PRINTK(args...)
> -#endif
> -
> -
> -/*------------------------------------------------------------------------
> - .
> - . The internal workings of the driver. If you are changing anything
> - . here with the SMC stuff, you should have the datasheet and know
> - . what you are doing.
> - .
> - -------------------------------------------------------------------------*/
> -
> -/* Memory sizing constant */
> -#define LAN91C111_MEMORY_MULTIPLIER (1024*2)
> -
> -#ifndef CONFIG_SMC91111_BASE
> -#error "SMC91111 Base address must be passed to initialization funciton"
> -/* #define CONFIG_SMC91111_BASE 0x20000300 */
> -#endif
> -
> -#define SMC_DEV_NAME "SMC91111"
> -#define SMC_PHY_ADDR 0x0000
> -#define SMC_ALLOC_MAX_TRY 5
> -#define SMC_TX_TIMEOUT 30
> -
> -#define SMC_PHY_CLOCK_DELAY 1000
> -
> -#define ETH_ZLEN 60
> -
> -#ifdef CONFIG_SMC_USE_32_BIT
> -#define USE_32_BIT 1
> -#else
> -#undef USE_32_BIT
> -#endif
> -
> -#ifdef SHARED_RESOURCES
> -extern void swap_to(int device_id);
> -#else
> -# define swap_to(x)
> -#endif
> -
> -#ifndef CONFIG_SMC91111_EXT_PHY
> -static void smc_phy_configure(struct eth_device *dev);
> -#endif /* !CONFIG_SMC91111_EXT_PHY */
> -
> -/*
> - ------------------------------------------------------------
> - .
> - . Internal routines
> - .
> - ------------------------------------------------------------
> -*/
> -
> -#ifdef CONFIG_SMC_USE_IOFUNCS
> -/*
> - * input and output functions
> - *
> - * Implemented due to inx,outx macros accessing the device improperly
> - * and putting the device into an unkown state.
> - *
> - * For instance, on Sharp LPD7A400 SDK, affects were chip memory
> - * could not be free'd (hence the alloc failures), duplicate packets,
> - * packets being corrupt (shifted) on the wire, etc. Switching to the
> - * inx,outx functions fixed this problem.
> - */
> -
> -static inline word SMC_inw(struct eth_device *dev, dword offset)
> -{
> - word v;
> - v = *((volatile word*)(dev->iobase + offset));
> - barrier(); *(volatile u32*)(0xc0000000);
> - return v;
> -}
> -
> -static inline void SMC_outw(struct eth_device *dev, word value, dword offset)
> -{
> - *((volatile word*)(dev->iobase + offset)) = value;
> - barrier(); *(volatile u32*)(0xc0000000);
> -}
> -
> -static inline byte SMC_inb(struct eth_device *dev, dword offset)
> -{
> - word _w;
> -
> - _w = SMC_inw(dev, offset & ~((dword)1));
> - return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
> -}
> -
> -static inline void SMC_outb(struct eth_device *dev, byte value, dword offset)
> -{
> - word _w;
> -
> - _w = SMC_inw(dev, offset & ~((dword)1));
> - if (offset & 1)
> - *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) =
> - (value<<8) | (_w & 0x00ff);
> - else
> - *((volatile word*)(dev->iobase + offset)) =
> - value | (_w & 0xff00);
> -}
> -
> -static inline void SMC_insw(struct eth_device *dev, dword offset,
> - volatile uchar* buf, dword len)
> -{
> - volatile word *p = (volatile word *)buf;
> -
> - while (len-- > 0) {
> - *p++ = SMC_inw(dev, offset);
> - barrier();
> - *((volatile u32*)(0xc0000000));
> - }
> -}
> -
> -static inline void SMC_outsw(struct eth_device *dev, dword offset,
> - uchar* buf, dword len)
> -{
> - volatile word *p = (volatile word *)buf;
> -
> - while (len-- > 0) {
> - SMC_outw(dev, *p++, offset);
> - barrier();
> - *(volatile u32*)(0xc0000000);
> - }
> -}
> -#endif /* CONFIG_SMC_USE_IOFUNCS */
> -
> -/*
> - . A rather simple routine to print out a packet for debugging purposes.
> -*/
> -#if SMC_DEBUG > 2
> -static void print_packet( byte *, int );
> -#endif
> -
> -#define tx_done(dev) 1
> -
> -static int poll4int (struct eth_device *dev, byte mask, int timeout)
> -{
> - int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
> - int is_timeout = 0;
> - word old_bank = SMC_inw (dev, BSR_REG);
> -
> - PRINTK2 ("Polling...\n");
> - SMC_SELECT_BANK (dev, 2);
> - while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) {
> - if (get_timer (0) >= tmo) {
> - is_timeout = 1;
> - break;
> - }
> - }
> -
> - /* restore old bank selection */
> - SMC_SELECT_BANK (dev, old_bank);
> -
> - if (is_timeout)
> - return 1;
> - else
> - return 0;
> -}
> -
> -/* Only one release command at a time, please */
> -static inline void smc_wait_mmu_release_complete (struct eth_device *dev)
> -{
> - int count = 0;
> -
> - /* assume bank 2 selected */
> - while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
> - udelay(1); /* Wait until not busy */
> - if (++count > 200)
> - break;
> - }
> -}
> -
> -/*
> - . Function: smc_reset( void )
> - . Purpose:
> - . This sets the SMC91111 chip to its normal state, hopefully from whatever
> - . mess that any other DOS driver has put it in.
> - .
> - . Maybe I should reset more registers to defaults in here? SOFTRST should
> - . do that for me.
> - .
> - . Method:
> - . 1. send a SOFT RESET
> - . 2. wait for it to finish
> - . 3. enable autorelease mode
> - . 4. reset the memory management unit
> - . 5. clear all interrupts
> - .
> -*/
> -static void smc_reset (struct eth_device *dev)
> -{
> - PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
> -
> - /* This resets the registers mostly to defaults, but doesn't
> - affect EEPROM. That seems unnecessary */
> - SMC_SELECT_BANK (dev, 0);
> - SMC_outw (dev, RCR_SOFTRST, RCR_REG);
> -
> - /* Setup the Configuration Register */
> - /* This is necessary because the CONFIG_REG is not affected */
> - /* by a soft reset */
> -
> - SMC_SELECT_BANK (dev, 1);
> -#if defined(CONFIG_SMC91111_EXT_PHY)
> - SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
> -#else
> - SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG);
> -#endif
> -
> -
> - /* Release from possible power-down state */
> - /* Configuration register is not affected by Soft Reset */
> - SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN,
> - CONFIG_REG);
> -
> - SMC_SELECT_BANK (dev, 0);
> -
> - /* this should pause enough for the chip to be happy */
> - udelay(10);
> -
> - /* Disable transmit and receive functionality */
> - SMC_outw (dev, RCR_CLEAR, RCR_REG);
> - SMC_outw (dev, TCR_CLEAR, TCR_REG);
> -
> - /* set the control register */
> - SMC_SELECT_BANK (dev, 1);
> - SMC_outw (dev, CTL_DEFAULT, CTL_REG);
> -
> - /* Reset the MMU */
> - SMC_SELECT_BANK (dev, 2);
> - smc_wait_mmu_release_complete (dev);
> - SMC_outw (dev, MC_RESET, MMU_CMD_REG);
> - while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY)
> - udelay(1); /* Wait until not busy */
> -
> - /* Note: It doesn't seem that waiting for the MMU busy is needed here,
> - but this is a place where future chipsets _COULD_ break. Be wary
> - of issuing another MMU command right after this */
> -
> - /* Disable all interrupts */
> - SMC_outb (dev, 0, IM_REG);
> -}
> -
> -/*
> - . Function: smc_enable
> - . Purpose: let the chip talk to the outside work
> - . Method:
> - . 1. Enable the transmitter
> - . 2. Enable the receiver
> - . 3. Enable interrupts
> -*/
> -static void smc_enable(struct eth_device *dev)
> -{
> - PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
> - SMC_SELECT_BANK( dev, 0 );
> - /* see the header file for options in TCR/RCR DEFAULT*/
> - SMC_outw( dev, TCR_DEFAULT, TCR_REG );
> - SMC_outw( dev, RCR_DEFAULT, RCR_REG );
> -
> - /* clear MII_DIS */
> -/* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
> -}
> -
> -/*
> - . Function: smc_halt
> - . Purpose: closes down the SMC91xxx chip.
> - . Method:
> - . 1. zero the interrupt mask
> - . 2. clear the enable receive flag
> - . 3. clear the enable xmit flags
> - .
> - . TODO:
> - . (1) maybe utilize power down mode.
> - . Why not yet? Because while the chip will go into power down mode,
> - . the manual says that it will wake up in response to any I/O requests
> - . in the register space. Empirical results do not show this working.
> -*/
> -static void smc_halt(struct eth_device *dev)
> -{
> - PRINTK2("%s: smc_halt\n", SMC_DEV_NAME);
> -
> - /* no more interrupts for me */
> - SMC_SELECT_BANK( dev, 2 );
> - SMC_outb( dev, 0, IM_REG );
> -
> - /* and tell the card to stay away from that nasty outside world */
> - SMC_SELECT_BANK( dev, 0 );
> - SMC_outb( dev, RCR_CLEAR, RCR_REG );
> - SMC_outb( dev, TCR_CLEAR, TCR_REG );
> -
> - swap_to(FLASH);
> -}
> -
> -
> -/*
> - . Function: smc_send(struct net_device * )
> - . Purpose:
> - . This sends the actual packet to the SMC9xxx chip.
> - .
> - . Algorithm:
> - . First, see if a saved_skb is available.
> - . ( this should NOT be called if there is no 'saved_skb'
> - . Now, find the packet number that the chip allocated
> - . Point the data pointers at it in memory
> - . Set the length word in the chip's memory
> - . Dump the packet to chip memory
> - . Check if a last byte is needed ( odd length packet )
> - . if so, set the control flag right
> - . Tell the card to send it
> - . Enable the transmit interrupt, so I know if it failed
> - . Free the kernel data if I actually sent it.
> -*/
> -static int smc_send(struct eth_device *dev, void *packet, int packet_length)
> -{
> - byte packet_no;
> - byte *buf;
> - int length;
> - int numPages;
> - int try = 0;
> - int time_out;
> - byte status;
> - byte saved_pnr;
> - word saved_ptr;
> -
> - /* save PTR and PNR registers before manipulation */
> - SMC_SELECT_BANK (dev, 2);
> - saved_pnr = SMC_inb( dev, PN_REG );
> - saved_ptr = SMC_inw( dev, PTR_REG );
> -
> - PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
> -
> - length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
> -
> - /* allocate memory
> - ** The MMU wants the number of pages to be the number of 256 bytes
> - ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
> - **
> - ** The 91C111 ignores the size bits, but the code is left intact
> - ** for backwards and future compatibility.
> - **
> - ** Pkt size for allocating is data length +6 (for additional status
> - ** words, length and ctl!)
> - **
> - ** If odd size then last byte is included in this header.
> - */
> - numPages = ((length & 0xfffe) + 6);
> - numPages >>= 8; /* Divide by 256 */
> -
> - if (numPages > 7) {
> - printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
> - return 0;
> - }
> -
> - /* now, try to allocate the memory */
> - SMC_SELECT_BANK (dev, 2);
> - SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG);
> -
> - /* FIXME: the ALLOC_INT bit never gets set *
> - * so the following will always give a *
> - * memory allocation error. *
> - * same code works in armboot though *
> - * -ro
> - */
> -
> -again:
> - try++;
> - time_out = MEMORY_WAIT_TIME;
> - do {
> - status = SMC_inb (dev, SMC91111_INT_REG);
> - if (status & IM_ALLOC_INT) {
> - /* acknowledge the interrupt */
> - SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG);
> - break;
> - }
> - } while (--time_out);
> -
> - if (!time_out) {
> - PRINTK2 ("%s: memory allocation, try %d failed ...\n",
> - SMC_DEV_NAME, try);
> - if (try < SMC_ALLOC_MAX_TRY)
> - goto again;
> - else
> - return 0;
> - }
> -
> - PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
> - SMC_DEV_NAME, try);
> -
> - buf = (byte *) packet;
> -
> - /* If I get here, I _know_ there is a packet slot waiting for me */
> - packet_no = SMC_inb (dev, AR_REG);
> - if (packet_no & AR_FAILED) {
> - /* or isn't there? BAD CHIP! */
> - printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
> - return 0;
> - }
> -
> - /* we have a packet address, so tell the card to use it */
> - SMC_outb (dev, packet_no, PN_REG);
> -
> - /* do not write new ptr value if Write data fifo not empty */
> - while ( saved_ptr & PTR_NOTEMPTY )
> - printf ("Write data fifo not empty!\n");
> -
> - /* point to the beginning of the packet */
> - SMC_outw (dev, PTR_AUTOINC, PTR_REG);
> -
> - PRINTK3 ("%s: Trying to xmit packet of length %x\n",
> - SMC_DEV_NAME, length);
> -
> -#if SMC_DEBUG > 2
> - printf ("Transmitting Packet\n");
> - print_packet (buf, length);
> -#endif
> -
> - /* send the packet length ( +6 for status, length and ctl byte )
> - and the status word ( set to zeros ) */
> -#ifdef USE_32_BIT
> - SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG);
> -#else
> - SMC_outw (dev, 0, SMC91111_DATA_REG);
> - /* send the packet length ( +6 for status words, length, and ctl */
> - SMC_outw (dev, (length + 6), SMC91111_DATA_REG);
> -#endif
> -
> - /* send the actual data
> - . I _think_ it's faster to send the longs first, and then
> - . mop up by sending the last word. It depends heavily
> - . on alignment, at least on the 486. Maybe it would be
> - . a good idea to check which is optimal? But that could take
> - . almost as much time as is saved?
> - */
> -#ifdef USE_32_BIT
> - SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2);
> - if (length & 0x2)
> - SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))),
> - SMC91111_DATA_REG);
> -#else
> - SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1);
> -#endif /* USE_32_BIT */
> -
> - /* Send the last byte, if there is one. */
> - if ((length & 1) == 0) {
> - SMC_outw (dev, 0, SMC91111_DATA_REG);
> - } else {
> - SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG);
> - }
> -
> - /* and let the chipset deal with it */
> - SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG);
> -
> - /* poll for TX INT */
> - /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */
> - /* poll for TX_EMPTY INT - autorelease enabled */
> - if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
> - /* sending failed */
> - PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
> -
> - /* release packet */
> - /* no need to release, MMU does that now */
> -
> - /* wait for MMU getting ready (low) */
> - while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
> - udelay(10);
> - }
> -
> - PRINTK2 ("MMU ready\n");
> -
> -
> - return 0;
> - } else {
> - /* ack. int */
> - SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG);
> - /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
> - PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
> - length);
> -
> - /* release packet */
> - /* no need to release, MMU does that now */
> -
> - /* wait for MMU getting ready (low) */
> - while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
> - udelay(10);
> - }
> -
> - PRINTK2 ("MMU ready\n");
> -
> -
> - }
> -
> - /* restore previously saved registers */
> - SMC_outb( dev, saved_pnr, PN_REG );
> - SMC_outw( dev, saved_ptr, PTR_REG );
> -
> - return length;
> -}
> -
> -static int smc_write_hwaddr(struct eth_device *dev)
> -{
> - int i;
> -
> - swap_to(ETHERNET);
> - SMC_SELECT_BANK (dev, 1);
> -#ifdef USE_32_BIT
> - for (i = 0; i < 6; i += 2) {
> - word address;
> -
> - address = dev->enetaddr[i + 1] << 8;
> - address |= dev->enetaddr[i];
> - SMC_outw(dev, address, (ADDR0_REG + i));
> - }
> -#else
> - for (i = 0; i < 6; i++)
> - SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
> -#endif
> - swap_to(FLASH);
> - return 0;
> -}
> -
> -/*
> - * Open and Initialize the board
> - *
> - * Set up everything, reset the card, etc ..
> - *
> - */
> -static int smc_init(struct eth_device *dev, struct bd_info *bd)
> -{
> - swap_to(ETHERNET);
> -
> - PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
> -
> - /* reset the hardware */
> - smc_reset (dev);
> - smc_enable (dev);
> -
> - /* Configure the PHY */
> -#ifndef CONFIG_SMC91111_EXT_PHY
> - smc_phy_configure (dev);
> -#endif
> -
> - /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
> -/* SMC_SELECT_BANK(dev, 0); */
> -/* SMC_outw(dev, 0, RPC_REG); */
> -
> - printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
> -
> - return 0;
> -}
> -
> -/*-------------------------------------------------------------
> - .
> - . smc_rcv - receive a packet from the card
> - .
> - . There is ( at least ) a packet waiting to be read from
> - . chip-memory.
> - .
> - . o Read the status
> - . o If an error, record it
> - . o otherwise, read in the packet
> - --------------------------------------------------------------
> -*/
> -static int smc_rcv(struct eth_device *dev)
> -{
> - int packet_number;
> - word status;
> - word packet_length;
> - int is_error = 0;
> -#ifdef USE_32_BIT
> - dword stat_len;
> -#endif
> - byte saved_pnr;
> - word saved_ptr;
> -
> - SMC_SELECT_BANK(dev, 2);
> - /* save PTR and PTR registers */
> - saved_pnr = SMC_inb( dev, PN_REG );
> - saved_ptr = SMC_inw( dev, PTR_REG );
> -
> - packet_number = SMC_inw( dev, RXFIFO_REG );
> -
> - if ( packet_number & RXFIFO_REMPTY ) {
> -
> - return 0;
> - }
> -
> - PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
> - /* start reading from the start of the packet */
> - SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
> -
> - /* First two words are status and packet_length */
> -#ifdef USE_32_BIT
> - stat_len = SMC_inl(dev, SMC91111_DATA_REG);
> - status = stat_len & 0xffff;
> - packet_length = stat_len >> 16;
> -#else
> - status = SMC_inw( dev, SMC91111_DATA_REG );
> - packet_length = SMC_inw( dev, SMC91111_DATA_REG );
> -#endif
> -
> - packet_length &= 0x07ff; /* mask off top bits */
> -
> - PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
> -
> - if ( !(status & RS_ERRORS ) ){
> - /* Adjust for having already read the first two words */
> - packet_length -= 4; /*4; */
> -
> -
> - /* set odd length for bug in LAN91C111, */
> - /* which never sets RS_ODDFRAME */
> - /* TODO ? */
> -
> -
> -#ifdef USE_32_BIT
> - PRINTK3(" Reading %d dwords (and %d bytes)\n",
> - packet_length >> 2, packet_length & 3 );
> - /* QUESTION: Like in the TX routine, do I want
> - to send the DWORDs or the bytes first, or some
> - mixture. A mixture might improve already slow PIO
> - performance */
> - SMC_insl(dev, SMC91111_DATA_REG, net_rx_packets[0],
> - packet_length >> 2);
> - /* read the left over bytes */
> - if (packet_length & 3) {
> - int i;
> -
> - byte *tail = (byte *)(net_rx_packets[0] +
> - (packet_length & ~3));
> - dword leftover = SMC_inl(dev, SMC91111_DATA_REG);
> - for (i=0; i<(packet_length & 3); i++)
> - *tail++ = (byte) (leftover >> (8*i)) & 0xff;
> - }
> -#else
> - PRINTK3(" Reading %d words and %d byte(s)\n",
> - (packet_length >> 1 ), packet_length & 1 );
> - SMC_insw(dev, SMC91111_DATA_REG , net_rx_packets[0],
> - packet_length >> 1);
> -
> -#endif /* USE_32_BIT */
> -
> -#if SMC_DEBUG > 2
> - printf("Receiving Packet\n");
> - print_packet(net_rx_packets[0], packet_length);
> -#endif
> - } else {
> - /* error ... */
> - /* TODO ? */
> - is_error = 1;
> - }
> -
> - while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
> - udelay(1); /* Wait until not busy */
> -
> - /* error or good, tell the card to get rid of this packet */
> - SMC_outw( dev, MC_RELEASE, MMU_CMD_REG );
> -
> - while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
> - udelay(1); /* Wait until not busy */
> -
> - /* restore saved registers */
> - SMC_outb( dev, saved_pnr, PN_REG );
> - SMC_outw( dev, saved_ptr, PTR_REG );
> -
> - if (!is_error) {
> - /* Pass the packet up to the protocol layers. */
> - net_process_received_packet(net_rx_packets[0], packet_length);
> - return packet_length;
> - } else {
> - return 0;
> - }
> -
> -}
> -
> -
> -#if 0
> -/*------------------------------------------------------------
> - . Modify a bit in the LAN91C111 register set
> - .-------------------------------------------------------------*/
> -static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg,
> - unsigned int bit, int val)
> -{
> - word regval;
> -
> - SMC_SELECT_BANK( dev, bank );
> -
> - regval = SMC_inw( dev, reg );
> - if (val)
> - regval |= bit;
> - else
> - regval &= ~bit;
> -
> - SMC_outw( dev, regval, 0 );
> - return(regval);
> -}
> -
> -
> -/*------------------------------------------------------------
> - . Retrieve a bit in the LAN91C111 register set
> - .-------------------------------------------------------------*/
> -static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit)
> -{
> - SMC_SELECT_BANK( dev, bank );
> - if ( SMC_inw( dev, reg ) & bit)
> - return(1);
> - else
> - return(0);
> -}
> -
> -
> -/*------------------------------------------------------------
> - . Modify a LAN91C111 register (word access only)
> - .-------------------------------------------------------------*/
> -static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val)
> -{
> - SMC_SELECT_BANK( dev, bank );
> - SMC_outw( dev, val, reg );
> -}
> -
> -
> -/*------------------------------------------------------------
> - . Retrieve a LAN91C111 register (word access only)
> - .-------------------------------------------------------------*/
> -static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg)
> -{
> - SMC_SELECT_BANK( dev, bank );
> - return(SMC_inw( dev, reg ));
> -}
> -
> -#endif /* 0 */
> -
> -/*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
> -
> -#if (SMC_DEBUG > 2 )
> -
> -/*------------------------------------------------------------
> - . Debugging function for viewing MII Management serial bitstream
> - .-------------------------------------------------------------*/
> -static void smc_dump_mii_stream (byte * bits, int size)
> -{
> - int i;
> -
> - printf ("BIT#:");
> - for (i = 0; i < size; ++i) {
> - printf ("%d", i % 10);
> - }
> -
> - printf ("\nMDOE:");
> - for (i = 0; i < size; ++i) {
> - if (bits[i] & MII_MDOE)
> - printf ("1");
> - else
> - printf ("0");
> - }
> -
> - printf ("\nMDO :");
> - for (i = 0; i < size; ++i) {
> - if (bits[i] & MII_MDO)
> - printf ("1");
> - else
> - printf ("0");
> - }
> -
> - printf ("\nMDI :");
> - for (i = 0; i < size; ++i) {
> - if (bits[i] & MII_MDI)
> - printf ("1");
> - else
> - printf ("0");
> - }
> -
> - printf ("\n");
> -}
> -#endif
> -
> -/*------------------------------------------------------------
> - . Reads a register from the MII Management serial interface
> - .-------------------------------------------------------------*/
> -#ifndef CONFIG_SMC91111_EXT_PHY
> -static word smc_read_phy_register (struct eth_device *dev, byte phyreg)
> -{
> - int oldBank;
> - int i;
> - byte mask;
> - word mii_reg;
> - byte bits[64];
> - int clk_idx = 0;
> - int input_idx;
> - word phydata;
> - byte phyaddr = SMC_PHY_ADDR;
> -
> - /* 32 consecutive ones on MDO to establish sync */
> - for (i = 0; i < 32; ++i)
> - bits[clk_idx++] = MII_MDOE | MII_MDO;
> -
> - /* Start code <01> */
> - bits[clk_idx++] = MII_MDOE;
> - bits[clk_idx++] = MII_MDOE | MII_MDO;
> -
> - /* Read command <10> */
> - bits[clk_idx++] = MII_MDOE | MII_MDO;
> - bits[clk_idx++] = MII_MDOE;
> -
> - /* Output the PHY address, msb first */
> - mask = (byte) 0x10;
> - for (i = 0; i < 5; ++i) {
> - if (phyaddr & mask)
> - bits[clk_idx++] = MII_MDOE | MII_MDO;
> - else
> - bits[clk_idx++] = MII_MDOE;
> -
> - /* Shift to next lowest bit */
> - mask >>= 1;
> - }
> -
> - /* Output the phy register number, msb first */
> - mask = (byte) 0x10;
> - for (i = 0; i < 5; ++i) {
> - if (phyreg & mask)
> - bits[clk_idx++] = MII_MDOE | MII_MDO;
> - else
> - bits[clk_idx++] = MII_MDOE;
> -
> - /* Shift to next lowest bit */
> - mask >>= 1;
> - }
> -
> - /* Tristate and turnaround (2 bit times) */
> - bits[clk_idx++] = 0;
> - /*bits[clk_idx++] = 0; */
> -
> - /* Input starts at this bit time */
> - input_idx = clk_idx;
> -
> - /* Will input 16 bits */
> - for (i = 0; i < 16; ++i)
> - bits[clk_idx++] = 0;
> -
> - /* Final clock bit */
> - bits[clk_idx++] = 0;
> -
> - /* Save the current bank */
> - oldBank = SMC_inw (dev, BANK_SELECT);
> -
> - /* Select bank 3 */
> - SMC_SELECT_BANK (dev, 3);
> -
> - /* Get the current MII register value */
> - mii_reg = SMC_inw (dev, MII_REG);
> -
> - /* Turn off all MII Interface bits */
> - mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
> -
> - /* Clock all 64 cycles */
> - for (i = 0; i < sizeof bits; ++i) {
> - /* Clock Low - output data */
> - SMC_outw (dev, mii_reg | bits[i], MII_REG);
> - udelay(SMC_PHY_CLOCK_DELAY);
> -
> -
> - /* Clock Hi - input data */
> - SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
> - udelay(SMC_PHY_CLOCK_DELAY);
> - bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
> - }
> -
> - /* Return to idle state */
> - /* Set clock to low, data to low, and output tristated */
> - SMC_outw (dev, mii_reg, MII_REG);
> - udelay(SMC_PHY_CLOCK_DELAY);
> -
> - /* Restore original bank select */
> - SMC_SELECT_BANK (dev, oldBank);
> -
> - /* Recover input data */
> - phydata = 0;
> - for (i = 0; i < 16; ++i) {
> - phydata <<= 1;
> -
> - if (bits[input_idx++] & MII_MDI)
> - phydata |= 0x0001;
> - }
> -
> -#if (SMC_DEBUG > 2 )
> - printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
> - phyaddr, phyreg, phydata);
> - smc_dump_mii_stream (bits, sizeof bits);
> -#endif
> -
> - return (phydata);
> -}
> -
> -
> -/*------------------------------------------------------------
> - . Writes a register to the MII Management serial interface
> - .-------------------------------------------------------------*/
> -static void smc_write_phy_register (struct eth_device *dev, byte phyreg,
> - word phydata)
> -{
> - int oldBank;
> - int i;
> - word mask;
> - word mii_reg;
> - byte bits[65];
> - int clk_idx = 0;
> - byte phyaddr = SMC_PHY_ADDR;
> -
> - /* 32 consecutive ones on MDO to establish sync */
> - for (i = 0; i < 32; ++i)
> - bits[clk_idx++] = MII_MDOE | MII_MDO;
> -
> - /* Start code <01> */
> - bits[clk_idx++] = MII_MDOE;
> - bits[clk_idx++] = MII_MDOE | MII_MDO;
> -
> - /* Write command <01> */
> - bits[clk_idx++] = MII_MDOE;
> - bits[clk_idx++] = MII_MDOE | MII_MDO;
> -
> - /* Output the PHY address, msb first */
> - mask = (byte) 0x10;
> - for (i = 0; i < 5; ++i) {
> - if (phyaddr & mask)
> - bits[clk_idx++] = MII_MDOE | MII_MDO;
> - else
> - bits[clk_idx++] = MII_MDOE;
> -
> - /* Shift to next lowest bit */
> - mask >>= 1;
> - }
> -
> - /* Output the phy register number, msb first */
> - mask = (byte) 0x10;
> - for (i = 0; i < 5; ++i) {
> - if (phyreg & mask)
> - bits[clk_idx++] = MII_MDOE | MII_MDO;
> - else
> - bits[clk_idx++] = MII_MDOE;
> -
> - /* Shift to next lowest bit */
> - mask >>= 1;
> - }
> -
> - /* Tristate and turnaround (2 bit times) */
> - bits[clk_idx++] = 0;
> - bits[clk_idx++] = 0;
> -
> - /* Write out 16 bits of data, msb first */
> - mask = 0x8000;
> - for (i = 0; i < 16; ++i) {
> - if (phydata & mask)
> - bits[clk_idx++] = MII_MDOE | MII_MDO;
> - else
> - bits[clk_idx++] = MII_MDOE;
> -
> - /* Shift to next lowest bit */
> - mask >>= 1;
> - }
> -
> - /* Final clock bit (tristate) */
> - bits[clk_idx++] = 0;
> -
> - /* Save the current bank */
> - oldBank = SMC_inw (dev, BANK_SELECT);
> -
> - /* Select bank 3 */
> - SMC_SELECT_BANK (dev, 3);
> -
> - /* Get the current MII register value */
> - mii_reg = SMC_inw (dev, MII_REG);
> -
> - /* Turn off all MII Interface bits */
> - mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
> -
> - /* Clock all cycles */
> - for (i = 0; i < sizeof bits; ++i) {
> - /* Clock Low - output data */
> - SMC_outw (dev, mii_reg | bits[i], MII_REG);
> - udelay(SMC_PHY_CLOCK_DELAY);
> -
> -
> - /* Clock Hi - input data */
> - SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
> - udelay(SMC_PHY_CLOCK_DELAY);
> - bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
> - }
> -
> - /* Return to idle state */
> - /* Set clock to low, data to low, and output tristated */
> - SMC_outw (dev, mii_reg, MII_REG);
> - udelay(SMC_PHY_CLOCK_DELAY);
> -
> - /* Restore original bank select */
> - SMC_SELECT_BANK (dev, oldBank);
> -
> -#if (SMC_DEBUG > 2 )
> - printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
> - phyaddr, phyreg, phydata);
> - smc_dump_mii_stream (bits, sizeof bits);
> -#endif
> -}
> -#endif /* !CONFIG_SMC91111_EXT_PHY */
> -
> -
> -/*------------------------------------------------------------
> - . Configures the specified PHY using Autonegotiation. Calls
> - . smc_phy_fixed() if the user has requested a certain config.
> - .-------------------------------------------------------------*/
> -#ifndef CONFIG_SMC91111_EXT_PHY
> -static void smc_phy_configure (struct eth_device *dev)
> -{
> - int timeout;
> - word my_phy_caps; /* My PHY capabilities */
> - word my_ad_caps; /* My Advertised capabilities */
> - word status = 0; /*;my status = 0 */
> -
> - PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME);
> -
> - /* Reset the PHY, setting all other bits to zero */
> - smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST);
> -
> - /* Wait for the reset to complete, or time out */
> - timeout = 6; /* Wait up to 3 seconds */
> - while (timeout--) {
> - if (!(smc_read_phy_register (dev, PHY_CNTL_REG)
> - & PHY_CNTL_RST)) {
> - /* reset complete */
> - break;
> - }
> -
> - mdelay(500); /* wait 500 millisecs */
> - }
> -
> - if (timeout < 1) {
> - printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
> - goto smc_phy_configure_exit;
> - }
> -
> - /* Read PHY Register 18, Status Output */
> - /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
> -
> - /* Enable PHY Interrupts (for register 18) */
> - /* Interrupts listed here are disabled */
> - smc_write_phy_register (dev, PHY_MASK_REG, 0xffff);
> -
> - /* Configure the Receive/Phy Control register */
> - SMC_SELECT_BANK (dev, 0);
> - SMC_outw (dev, RPC_DEFAULT, RPC_REG);
> -
> - /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
> - my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG);
> - my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
> -
> - if (my_phy_caps & PHY_STAT_CAP_T4)
> - my_ad_caps |= PHY_AD_T4;
> -
> - if (my_phy_caps & PHY_STAT_CAP_TXF)
> - my_ad_caps |= PHY_AD_TX_FDX;
> -
> - if (my_phy_caps & PHY_STAT_CAP_TXH)
> - my_ad_caps |= PHY_AD_TX_HDX;
> -
> - if (my_phy_caps & PHY_STAT_CAP_TF)
> - my_ad_caps |= PHY_AD_10_FDX;
> -
> - if (my_phy_caps & PHY_STAT_CAP_TH)
> - my_ad_caps |= PHY_AD_10_HDX;
> -
> - /* Update our Auto-Neg Advertisement Register */
> - smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps);
> -
> - /* Read the register back. Without this, it appears that when */
> - /* auto-negotiation is restarted, sometimes it isn't ready and */
> - /* the link does not come up. */
> - smc_read_phy_register(dev, PHY_AD_REG);
> -
> - PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
> - PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
> -
> - /* Restart auto-negotiation process in order to advertise my caps */
> - smc_write_phy_register (dev, PHY_CNTL_REG,
> - PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
> -
> - /* Wait for the auto-negotiation to complete. This may take from */
> - /* 2 to 3 seconds. */
> - /* Wait for the reset to complete, or time out */
> - timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
> - while (timeout--) {
> -
> - status = smc_read_phy_register (dev, PHY_STAT_REG);
> - if (status & PHY_STAT_ANEG_ACK) {
> - /* auto-negotiate complete */
> - break;
> - }
> -
> - mdelay(500); /* wait 500 millisecs */
> -
> - /* Restart auto-negotiation if remote fault */
> - if (status & PHY_STAT_REM_FLT) {
> - printf ("%s: PHY remote fault detected\n",
> - SMC_DEV_NAME);
> -
> - /* Restart auto-negotiation */
> - printf ("%s: PHY restarting auto-negotiation\n",
> - SMC_DEV_NAME);
> - smc_write_phy_register (dev, PHY_CNTL_REG,
> - PHY_CNTL_ANEG_EN |
> - PHY_CNTL_ANEG_RST |
> - PHY_CNTL_SPEED |
> - PHY_CNTL_DPLX);
> - }
> - }
> -
> - if (timeout < 1) {
> - printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME);
> - }
> -
> - /* Fail if we detected an auto-negotiate remote fault */
> - if (status & PHY_STAT_REM_FLT) {
> - printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME);
> - }
> -
> - /* Re-Configure the Receive/Phy Control register */
> - SMC_outw (dev, RPC_DEFAULT, RPC_REG);
> -
> -smc_phy_configure_exit: ;
> -
> -}
> -#endif /* !CONFIG_SMC91111_EXT_PHY */
> -
> -
> -#if SMC_DEBUG > 2
> -static void print_packet( byte * buf, int length )
> -{
> - int i;
> - int remainder;
> - int lines;
> -
> - printf("Packet of length %d \n", length );
> -
> -#if SMC_DEBUG > 3
> - lines = length / 16;
> - remainder = length % 16;
> -
> - for ( i = 0; i < lines ; i ++ ) {
> - int cur;
> -
> - for ( cur = 0; cur < 8; cur ++ ) {
> - byte a, b;
> -
> - a = *(buf ++ );
> - b = *(buf ++ );
> - printf("%02x%02x ", a, b );
> - }
> - printf("\n");
> - }
> - for ( i = 0; i < remainder/2 ; i++ ) {
> - byte a, b;
> -
> - a = *(buf ++ );
> - b = *(buf ++ );
> - printf("%02x%02x ", a, b );
> - }
> - printf("\n");
> -#endif
> -}
> -#endif
> -
> -int smc91111_initialize(u8 dev_num, phys_addr_t base_addr)
> -{
> - struct smc91111_priv *priv;
> - struct eth_device *dev;
> - int i;
> -
> - priv = malloc(sizeof(*priv));
> - if (!priv)
> - return 0;
> - dev = malloc(sizeof(*dev));
> - if (!dev) {
> - free(priv);
> - return 0;
> - }
> -
> - memset(dev, 0, sizeof(*dev));
> - priv->dev_num = dev_num;
> - dev->priv = priv;
> - dev->iobase = base_addr;
> -
> - swap_to(ETHERNET);
> - SMC_SELECT_BANK(dev, 1);
> - for (i = 0; i < 6; ++i)
> - dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i));
> - swap_to(FLASH);
> -
> - dev->init = smc_init;
> - dev->halt = smc_halt;
> - dev->send = smc_send;
> - dev->recv = smc_rcv;
> - dev->write_hwaddr = smc_write_hwaddr;
> - sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);
> -
> - eth_register(dev);
> - return 0;
> -}
> diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h
> deleted file mode 100644
> index f2ba34474598..000000000000
> --- a/drivers/net/smc91111.h
> +++ /dev/null
> @@ -1,632 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*------------------------------------------------------------------------
> - . smc91111.h - macros for the LAN91C111 Ethernet Driver
> - .
> - . (C) Copyright 2002
> - . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> - . Rolf Offermanns <rof at sysgo.de>
> - . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
> - . Developed by Simple Network Magic Corporation (SNMC)
> - . Copyright (C) 1996 by Erik Stahlman (ES)
> - .
> - . This file contains register information and access macros for
> - . the LAN91C111 single chip ethernet controller. It is a modified
> - . version of the smc9194.h file.
> - .
> - . Information contained in this file was obtained from the LAN91C111
> - . manual from SMC. To get a copy, if you really want one, you can find
> - . information under www.smsc.com.
> - .
> - . Authors
> - . Erik Stahlman ( erik at vt.edu )
> - . Daris A Nevil ( dnevil at snmc.com )
> - .
> - . History
> - . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device
> - .
> - ---------------------------------------------------------------------------*/
> -#ifndef _SMC91111_H_
> -#define _SMC91111_H_
> -
> -#include <asm/types.h>
> -#include <config.h>
> -#include <net.h>
> -
> -/*
> - * This function may be called by the board specific initialisation code
> - * in order to override the default mac address.
> - */
> -
> -void smc_set_mac_addr (const unsigned char *addr);
> -
> -
> -/* I want some simple types */
> -
> -typedef unsigned char byte;
> -typedef unsigned short word;
> -typedef unsigned long int dword;
> -
> -struct smc91111_priv{
> - u8 dev_num;
> -};
> -
> -/*
> - . DEBUGGING LEVELS
> - .
> - . 0 for normal operation
> - . 1 for slightly more details
> - . >2 for various levels of increasingly useless information
> - . 2 for interrupt tracking, status flags
> - . 3 for packet info
> - . 4 for complete packet dumps
> -*/
> -/*#define SMC_DEBUG 0 */
> -
> -/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
> -
> -#define SMC_IO_EXTENT 16
> -
> -#if defined(CONFIG_MS7206SE)
> -#define SWAB7206(x) ({ word __x = x; ((__x << 8)|(__x >> 8)); })
> -#define SMC_inw(a, r) *((volatile word*)((a)->iobase + (r)))
> -#define SMC_inb(a, r) (*((volatile byte*)((a)->iobase + ((r) ^ 0x01))))
> -#define SMC_insw(a, r, b, l) \
> - do { \
> - int __i; \
> - word *__b2 = (word *)(b); \
> - for (__i = 0; __i < (l); __i++) { \
> - *__b2++ = SWAB7206(SMC_inw(a, r)); \
> - } \
> - } while (0)
> -#define SMC_outw(a, d, r) (*((volatile word *)((a)->iobase+(r))) = d)
> -#define SMC_outb(a, d, r) ({ word __d = (byte)(d); \
> - word __w = SMC_inw((a), ((r)&(~1))); \
> - if (((r) & 1)) \
> - __w = (__w & 0x00ff) | (__d << 8); \
> - else \
> - __w = (__w & 0xff00) | (__d); \
> - SMC_outw((a), __w, ((r)&(~1))); \
> - })
> -#define SMC_outsw(a, r, b, l) \
> - do { \
> - int __i; \
> - word *__b2 = (word *)(b); \
> - for (__i = 0; __i < (l); __i++) { \
> - SMC_outw(a, SWAB7206(*__b2), r); \
> - __b2++; \
> - } \
> - } while (0)
> -#else
> -
> -#ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */
> -/*
> - * We have only 16 Bit PCMCIA access on Socket 0
> - */
> -
> -#if CONFIG_ARM64
> -#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r)))))
> -#else
> -#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r))))
> -#endif
> -#define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF))
> -
> -#if CONFIG_ARM64
> -#define SMC_outw(a, d, r) \
> - (*((volatile word*)((a)->iobase+((dword)(r)))) = d)
> -#else
> -#define SMC_outw(a, d, r) \
> - (*((volatile word*)((a)->iobase+(r))) = d)
> -#endif
> -#define SMC_outb(a,d,r) ({ word __d = (byte)(d); \
> - word __w = SMC_inw((a),(r)&~1); \
> - __w &= ((r)&1) ? 0x00FF : 0xFF00; \
> - __w |= ((r)&1) ? __d<<8 : __d; \
> - SMC_outw((a),__w,(r)&~1); \
> - })
> -#if 0
> -#define SMC_outsw(a,r,b,l) outsw((a)->iobase+(r), (b), (l))
> -#else
> -#define SMC_outsw(a,r,b,l) ({ int __i; \
> - word *__b2; \
> - __b2 = (word *) b; \
> - for (__i = 0; __i < l; __i++) { \
> - SMC_outw((a), *(__b2 + __i), r); \
> - } \
> - })
> -#endif
> -
> -#if 0
> -#define SMC_insw(a,r,b,l) insw((a)->iobase+(r), (b), (l))
> -#else
> -#define SMC_insw(a,r,b,l) ({ int __i ; \
> - word *__b2; \
> - __b2 = (word *) b; \
> - for (__i = 0; __i < l; __i++) { \
> - *(__b2 + __i) = SMC_inw((a),(r)); \
> - SMC_inw((a),0); \
> - }; \
> - })
> -#endif
> -
> -#endif /* CONFIG_SMC_USE_IOFUNCS */
> -
> -#if defined(CONFIG_SMC_USE_32_BIT)
> -
> -#ifdef CONFIG_XSENGINE
> -#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1))))
> -#else
> -#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r))))
> -#endif
> -
> -#define SMC_insl(a,r,b,l) ({ int __i ; \
> - dword *__b2; \
> - __b2 = (dword *) b; \
> - for (__i = 0; __i < l; __i++) { \
> - *(__b2 + __i) = SMC_inl((a),(r)); \
> - SMC_inl((a),0); \
> - }; \
> - })
> -
> -#ifdef CONFIG_XSENGINE
> -#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d)
> -#else
> -#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d)
> -#endif
> -#define SMC_outsl(a,r,b,l) ({ int __i; \
> - dword *__b2; \
> - __b2 = (dword *) b; \
> - for (__i = 0; __i < l; __i++) { \
> - SMC_outl((a), *(__b2 + __i), r); \
> - } \
> - })
> -
> -#endif /* CONFIG_SMC_USE_32_BIT */
> -
> -#endif
> -
> -/*---------------------------------------------------------------
> - .
> - . A description of the SMSC registers is probably in order here,
> - . although for details, the SMC datasheet is invaluable.
> - .
> - . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
> - . are accessed by writing a number into the BANK_SELECT register
> - . ( I also use a SMC_SELECT_BANK macro for this ).
> - .
> - . The banks are configured so that for most purposes, bank 2 is all
> - . that is needed for simple run time tasks.
> - -----------------------------------------------------------------------*/
> -
> -/*
> - . Bank Select Register:
> - .
> - . yyyy yyyy 0000 00xx
> - . xx = bank number
> - . yyyy yyyy = 0x33, for identification purposes.
> -*/
> -#define BANK_SELECT 14
> -
> -/* Transmit Control Register */
> -/* BANK 0 */
> -#define TCR_REG 0x0000 /* transmit control register */
> -#define TCR_ENABLE 0x0001 /* When 1 we can transmit */
> -#define TCR_LOOP 0x0002 /* Controls output pin LBK */
> -#define TCR_FORCOL 0x0004 /* When 1 will force a collision */
> -#define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */
> -#define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */
> -#define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */
> -#define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */
> -#define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */
> -#define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */
> -#define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */
> -
> -#define TCR_CLEAR 0 /* do NOTHING */
> -/* the default settings for the TCR register : */
> -/* QUESTION: do I want to enable padding of short packets ? */
> -#define TCR_DEFAULT TCR_ENABLE
> -
> -
> -/* EPH Status Register */
> -/* BANK 0 */
> -#define EPH_STATUS_REG 0x0002
> -#define ES_TX_SUC 0x0001 /* Last TX was successful */
> -#define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */
> -#define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */
> -#define ES_LTX_MULT 0x0008 /* Last tx was a multicast */
> -#define ES_16COL 0x0010 /* 16 Collisions Reached */
> -#define ES_SQET 0x0020 /* Signal Quality Error Test */
> -#define ES_LTXBRD 0x0040 /* Last tx was a broadcast */
> -#define ES_TXDEFR 0x0080 /* Transmit Deferred */
> -#define ES_LATCOL 0x0200 /* Late collision detected on last tx */
> -#define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */
> -#define ES_EXC_DEF 0x0800 /* Excessive Deferral */
> -#define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */
> -#define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */
> -#define ES_TXUNRN 0x8000 /* Tx Underrun */
> -
> -
> -/* Receive Control Register */
> -/* BANK 0 */
> -#define RCR_REG 0x0004
> -#define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */
> -#define RCR_PRMS 0x0002 /* Enable promiscuous mode */
> -#define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */
> -#define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */
> -#define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */
> -#define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */
> -#define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */
> -#define RCR_SOFTRST 0x8000 /* resets the chip */
> -
> -/* the normal settings for the RCR register : */
> -#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
> -#define RCR_CLEAR 0x0 /* set it to a base state */
> -
> -/* Counter Register */
> -/* BANK 0 */
> -#define COUNTER_REG 0x0006
> -
> -/* Memory Information Register */
> -/* BANK 0 */
> -#define MIR_REG 0x0008
> -
> -/* Receive/Phy Control Register */
> -/* BANK 0 */
> -#define RPC_REG 0x000A
> -#define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */
> -#define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */
> -#define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */
> -#define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */
> -#define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */
> -#define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */
> -#define RPC_LED_RES (0x01) /* LED = Reserved */
> -#define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */
> -#define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */
> -#define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */
> -#define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */
> -#define RPC_LED_TX (0x06) /* LED = TX packet occurred */
> -#define RPC_LED_RX (0x07) /* LED = RX packet occurred */
> -#if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10)
> -/* buggy schematic: LEDa -> yellow, LEDb --> green */
> -#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
> - | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \
> - | (RPC_LED_100_10 << RPC_LSXB_SHFT) )
> -#else
> -/* SMSC reference design: LEDa --> green, LEDb --> yellow */
> -#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
> - | (RPC_LED_100_10 << RPC_LSXA_SHFT) \
> - | (RPC_LED_TX_RX << RPC_LSXB_SHFT) )
> -#endif
> -
> -/* Bank 0 0x000C is reserved */
> -
> -/* Bank Select Register */
> -/* All Banks */
> -#define BSR_REG 0x000E
> -
> -
> -/* Configuration Reg */
> -/* BANK 1 */
> -#define CONFIG_REG 0x0000
> -#define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */
> -#define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */
> -#define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */
> -#define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */
> -
> -/* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */
> -#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
> -
> -
> -/* Base Address Register */
> -/* BANK 1 */
> -#define BASE_REG 0x0002
> -
> -
> -/* Individual Address Registers */
> -/* BANK 1 */
> -#define ADDR0_REG 0x0004
> -#define ADDR1_REG 0x0006
> -#define ADDR2_REG 0x0008
> -
> -
> -/* General Purpose Register */
> -/* BANK 1 */
> -#define GP_REG 0x000A
> -
> -
> -/* Control Register */
> -/* BANK 1 */
> -#define CTL_REG 0x000C
> -#define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */
> -#define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */
> -#define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */
> -#define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */
> -#define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */
> -#define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */
> -#define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */
> -#define CTL_STORE 0x0001 /* When set stores registers into EEPROM */
> -#define CTL_DEFAULT (0x1A10) /* Autorelease enabled*/
> -
> -/* MMU Command Register */
> -/* BANK 2 */
> -#define MMU_CMD_REG 0x0000
> -#define MC_BUSY 1 /* When 1 the last release has not completed */
> -#define MC_NOP (0<<5) /* No Op */
> -#define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */
> -#define MC_RESET (2<<5) /* Reset MMU to initial state */
> -#define MC_REMOVE (3<<5) /* Remove the current rx packet */
> -#define MC_RELEASE (4<<5) /* Remove and release the current rx packet */
> -#define MC_FREEPKT (5<<5) /* Release packet in PNR register */
> -#define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */
> -#define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */
> -
> -
> -/* Packet Number Register */
> -/* BANK 2 */
> -#define PN_REG 0x0002
> -
> -
> -/* Allocation Result Register */
> -/* BANK 2 */
> -#define AR_REG 0x0003
> -#define AR_FAILED 0x80 /* Alocation Failed */
> -
> -
> -/* RX FIFO Ports Register */
> -/* BANK 2 */
> -#define RXFIFO_REG 0x0004 /* Must be read as a word */
> -#define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */
> -
> -
> -/* TX FIFO Ports Register */
> -/* BANK 2 */
> -#define TXFIFO_REG RXFIFO_REG /* Must be read as a word */
> -#define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */
> -
> -
> -/* Pointer Register */
> -/* BANK 2 */
> -#define PTR_REG 0x0006
> -#define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */
> -#define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */
> -#define PTR_READ 0x2000 /* When 1 the operation is a read */
> -#define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */
> -
> -
> -/* Data Register */
> -/* BANK 2 */
> -#define SMC91111_DATA_REG 0x0008
> -
> -
> -/* Interrupt Status/Acknowledge Register */
> -/* BANK 2 */
> -#define SMC91111_INT_REG 0x000C
> -
> -
> -/* Interrupt Mask Register */
> -/* BANK 2 */
> -#define IM_REG 0x000D
> -#define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */
> -#define IM_ERCV_INT 0x40 /* Early Receive Interrupt */
> -#define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */
> -#define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */
> -#define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */
> -#define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */
> -#define IM_TX_INT 0x02 /* Transmit Interrrupt */
> -#define IM_RCV_INT 0x01 /* Receive Interrupt */
> -
> -
> -/* Multicast Table Registers */
> -/* BANK 3 */
> -#define MCAST_REG1 0x0000
> -#define MCAST_REG2 0x0002
> -#define MCAST_REG3 0x0004
> -#define MCAST_REG4 0x0006
> -
> -
> -/* Management Interface Register (MII) */
> -/* BANK 3 */
> -#define MII_REG 0x0008
> -#define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */
> -#define MII_MDOE 0x0008 /* MII Output Enable */
> -#define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */
> -#define MII_MDI 0x0002 /* MII Input, pin MDI */
> -#define MII_MDO 0x0001 /* MII Output, pin MDO */
> -
> -
> -/* Revision Register */
> -/* BANK 3 */
> -#define REV_REG 0x000A /* ( hi: chip id low: rev # ) */
> -
> -
> -/* Early RCV Register */
> -/* BANK 3 */
> -/* this is NOT on SMC9192 */
> -#define ERCV_REG 0x000C
> -#define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */
> -#define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */
> -
> -/* External Register */
> -/* BANK 7 */
> -#define EXT_REG 0x0000
> -
> -
> -#define CHIP_9192 3
> -#define CHIP_9194 4
> -#define CHIP_9195 5
> -#define CHIP_9196 6
> -#define CHIP_91100 7
> -#define CHIP_91100FD 8
> -#define CHIP_91111FD 9
> -
> -#if 0
> -static const char * chip_ids[ 15 ] = {
> - NULL, NULL, NULL,
> - /* 3 */ "SMC91C90/91C92",
> - /* 4 */ "SMC91C94",
> - /* 5 */ "SMC91C95",
> - /* 6 */ "SMC91C96",
> - /* 7 */ "SMC91C100",
> - /* 8 */ "SMC91C100FD",
> - /* 9 */ "SMC91C111",
> - NULL, NULL,
> - NULL, NULL, NULL};
> -#endif
> -
> -/*
> - . Transmit status bits
> -*/
> -#define TS_SUCCESS 0x0001
> -#define TS_LOSTCAR 0x0400
> -#define TS_LATCOL 0x0200
> -#define TS_16COL 0x0010
> -
> -/*
> - . Receive status bits
> -*/
> -#define RS_ALGNERR 0x8000
> -#define RS_BRODCAST 0x4000
> -#define RS_BADCRC 0x2000
> -#define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */
> -#define RS_TOOLONG 0x0800
> -#define RS_TOOSHORT 0x0400
> -#define RS_MULTICAST 0x0001
> -#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
> -
> -
> -/* PHY Types */
> -enum {
> - PHY_LAN83C183 = 1, /* LAN91C111 Internal PHY */
> - PHY_LAN83C180
> -};
> -
> -
> -/* PHY Register Addresses (LAN91C111 Internal PHY) */
> -
> -/* PHY Control Register */
> -#define PHY_CNTL_REG 0x00
> -#define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */
> -#define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */
> -#define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */
> -#define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */
> -#define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */
> -#define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */
> -#define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */
> -#define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */
> -#define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */
> -
> -/* PHY Status Register */
> -#define PHY_STAT_REG 0x01
> -#define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */
> -#define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */
> -#define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */
> -#define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */
> -#define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */
> -#define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */
> -#define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */
> -#define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */
> -#define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */
> -#define PHY_STAT_LINK 0x0004 /* 1=valid link */
> -#define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */
> -#define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */
> -
> -/* PHY Identifier Registers */
> -#define PHY_ID1_REG 0x02 /* PHY Identifier 1 */
> -#define PHY_ID2_REG 0x03 /* PHY Identifier 2 */
> -
> -/* PHY Auto-Negotiation Advertisement Register */
> -#define PHY_AD_REG 0x04
> -#define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */
> -#define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */
> -#define PHY_AD_RF 0x2000 /* 1=advertise remote fault */
> -#define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */
> -#define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */
> -#define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */
> -#define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */
> -#define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */
> -#define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */
> -
> -/* PHY Auto-negotiation Remote End Capability Register */
> -#define PHY_RMT_REG 0x05
> -/* Uses same bit definitions as PHY_AD_REG */
> -
> -/* PHY Configuration Register 1 */
> -#define PHY_CFG1_REG 0x10
> -#define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */
> -#define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */
> -#define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */
> -#define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */
> -#define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */
> -#define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */
> -#define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */
> -#define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */
> -#define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */
> -#define PHY_CFG1_TLVL_MASK 0x003C
> -#define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */
> -
> -
> -/* PHY Configuration Register 2 */
> -#define PHY_CFG2_REG 0x11
> -#define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */
> -#define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */
> -#define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */
> -#define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */
> -
> -/* PHY Status Output (and Interrupt status) Register */
> -#define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */
> -#define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */
> -#define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */
> -#define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */
> -#define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */
> -#define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */
> -#define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */
> -#define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */
> -#define PHY_INT_JAB 0x0100 /* 1=Jabber detected */
> -#define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */
> -#define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */
> -
> -/* PHY Interrupt/Status Mask Register */
> -#define PHY_MASK_REG 0x13 /* Interrupt Mask */
> -/* Uses the same bit definitions as PHY_INT_REG */
> -
> -
> -/*-------------------------------------------------------------------------
> - . I define some macros to make it easier to do somewhat common
> - . or slightly complicated, repeated tasks.
> - --------------------------------------------------------------------------*/
> -
> -/* select a register bank, 0 to 3 */
> -
> -#define SMC_SELECT_BANK(a,x) { SMC_outw((a), (x), BANK_SELECT ); }
> -
> -/* this enables an interrupt in the interrupt mask register */
> -#define SMC_ENABLE_INT(a,x) {\
> - unsigned char mask;\
> - SMC_SELECT_BANK((a),2);\
> - mask = SMC_inb((a), IM_REG );\
> - mask |= (x);\
> - SMC_outb( (a), mask, IM_REG ); \
> -}
> -
> -/* this disables an interrupt from the interrupt mask register */
> -
> -#define SMC_DISABLE_INT(a,x) {\
> - unsigned char mask;\
> - SMC_SELECT_BANK(2);\
> - mask = SMC_inb( (a), IM_REG );\
> - mask &= ~(x);\
> - SMC_outb( (a), mask, IM_REG ); \
> -}
> -
> -/*----------------------------------------------------------------------
> - . Define the interrupts that I want to receive from the card
> - .
> - . I want:
> - . IM_EPH_INT, for nasty errors
> - . IM_RCV_INT, for happy received packets
> - . IM_RX_OVRN_INT, because I have to kick the receiver
> - . IM_MDINT, for PHY Register 18 Status Changes
> - --------------------------------------------------------------------------*/
> -#define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \
> - IM_MDINT)
> -
> -#endif /* _SMC_91111_H_ */
> diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile
> index d4be0c7350dc..5b48a9d43c62 100644
> --- a/examples/standalone/Makefile
> +++ b/examples/standalone/Makefile
> @@ -4,7 +4,6 @@
> # Wolfgang Denk, DENX Software Engineering, wd at denx.de.
>
> extra-y := hello_world
> -extra-$(CONFIG_SMC91111) += smc91111_eeprom
> extra-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2
> extra-$(CONFIG_PPC) += sched
>
> diff --git a/examples/standalone/smc91111_eeprom.c b/examples/standalone/smc91111_eeprom.c
> deleted file mode 100644
> index bf7e93064309..000000000000
> --- a/examples/standalone/smc91111_eeprom.c
> +++ /dev/null
> @@ -1,372 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * (C) Copyright 2004
> - * Robin Getz rgetz at blacfin.uclinux.org
> - *
> - * Heavily borrowed from the following peoples GPL'ed software:
> - * - Wolfgang Denk, DENX Software Engineering, wd at denx.de
> - * Das U-Boot
> - * - Ladislav Michl ladis at linux-mips.org
> - * A rejected patch on the U-Boot mailing list
> - */
> -
> -#include <common.h>
> -#include <exports.h>
> -#include <linux/delay.h>
> -#include "../drivers/net/smc91111.h"
> -
> -#ifndef SMC91111_EEPROM_INIT
> -# define SMC91111_EEPROM_INIT()
> -#endif
> -
> -#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
> -#define EEPROM 0x1
> -#define MAC 0x2
> -#define UNKNOWN 0x4
> -
> -void dump_reg (struct eth_device *dev);
> -void dump_eeprom (struct eth_device *dev);
> -int write_eeprom_reg (struct eth_device *dev, int value, int reg);
> -void copy_from_eeprom (struct eth_device *dev);
> -void print_MAC (struct eth_device *dev);
> -int read_eeprom_reg (struct eth_device *dev, int reg);
> -void print_macaddr (struct eth_device *dev);
> -
> -int smc91111_eeprom(int argc, char *const argv[])
> -{
> - int c, i, j, done, line, reg, value, start, what;
> - char input[50];
> -
> - struct eth_device dev;
> - dev.iobase = CONFIG_SMC91111_BASE;
> -
> - /* Print the ABI version */
> - app_startup (argv);
> - if (XF_VERSION != (int) get_version ()) {
> - printf ("Expects ABI version %d\n", XF_VERSION);
> - printf ("Actual U-Boot ABI version %d\n",
> - (int) get_version ());
> - printf ("Can't run\n\n");
> - return (0);
> - }
> -
> - SMC91111_EEPROM_INIT();
> -
> - if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
> - printf ("Can't find SMSC91111\n");
> - return (0);
> - }
> -
> - done = 0;
> - what = UNKNOWN;
> - printf ("\n");
> - while (!done) {
> - /* print the prompt */
> - printf ("SMC91111> ");
> - line = 0;
> - i = 0;
> - start = 1;
> - while (!line) {
> - /* Wait for a keystroke */
> - while (!tstc ());
> -
> - c = getc ();
> - /* Make Uppercase */
> - if (c >= 'Z')
> - c -= ('a' - 'A');
> - /* printf(" |%02x| ",c); */
> -
> - switch (c) {
> - case '\r': /* Enter */
> - case '\n':
> - input[i] = 0;
> - puts ("\r\n");
> - line = 1;
> - break;
> - case '\0': /* nul */
> - continue;
> -
> - case 0x03: /* ^C - break */
> - input[0] = 0;
> - i = 0;
> - line = 1;
> - done = 1;
> - break;
> -
> - case 0x5F:
> - case 0x08: /* ^H - backspace */
> - case 0x7F: /* DEL - backspace */
> - if (i > 0) {
> - puts ("\b \b");
> - i--;
> - }
> - break;
> - default:
> - if (start) {
> - if ((c == 'W') || (c == 'D')
> - || (c == 'M') || (c == 'C')
> - || (c == 'P')) {
> - putc (c);
> - input[i] = c;
> - if (i <= 45)
> - i++;
> - start = 0;
> - }
> - } else {
> - if ((c >= '0' && c <= '9')
> - || (c >= 'A' && c <= 'F')
> - || (c == 'E') || (c == 'M')
> - || (c == ' ')) {
> - putc (c);
> - input[i] = c;
> - if (i <= 45)
> - i++;
> - break;
> - }
> - }
> - break;
> - }
> - }
> -
> - for (; i < 49; i++)
> - input[i] = 0;
> -
> - switch (input[0]) {
> - case ('W'):
> - /* Line should be w reg value */
> - i = 0;
> - reg = 0;
> - value = 0;
> - /* Skip to the next space or end) */
> - while ((input[i] != ' ') && (input[i] != 0))
> - i++;
> -
> - if (input[i] != 0)
> - i++;
> -
> - /* Are we writing to EEPROM or MAC */
> - switch (input[i]) {
> - case ('E'):
> - what = EEPROM;
> - break;
> - case ('M'):
> - what = MAC;
> - break;
> - default:
> - what = UNKNOWN;
> - break;
> - }
> -
> - /* skip to the next space or end */
> - while ((input[i] != ' ') && (input[i] != 0))
> - i++;
> - if (input[i] != 0)
> - i++;
> -
> - /* Find register to write into */
> - j = 0;
> - while ((input[i] != ' ') && (input[i] != 0)) {
> - j = input[i] - 0x30;
> - if (j >= 0xA) {
> - j -= 0x07;
> - }
> - reg = (reg * 0x10) + j;
> - i++;
> - }
> -
> - while ((input[i] != ' ') && (input[i] != 0))
> - i++;
> -
> - if (input[i] != 0)
> - i++;
> - else
> - what = UNKNOWN;
> -
> - /* Get the value to write */
> - j = 0;
> - while ((input[i] != ' ') && (input[i] != 0)) {
> - j = input[i] - 0x30;
> - if (j >= 0xA) {
> - j -= 0x07;
> - }
> - value = (value * 0x10) + j;
> - i++;
> - }
> -
> - switch (what) {
> - case 1:
> - printf ("Writing EEPROM register %02x with %04x\n", reg, value);
> - write_eeprom_reg (&dev, value, reg);
> - break;
> - case 2:
> - printf ("Writing MAC register bank %i, reg %02x with %04x\n", reg >> 4, reg & 0xE, value);
> - SMC_SELECT_BANK (&dev, reg >> 4);
> - SMC_outw (&dev, value, reg & 0xE);
> - break;
> - default:
> - printf ("Wrong\n");
> - break;
> - }
> - break;
> - case ('D'):
> - dump_eeprom (&dev);
> - break;
> - case ('M'):
> - dump_reg (&dev);
> - break;
> - case ('C'):
> - copy_from_eeprom (&dev);
> - break;
> - case ('P'):
> - print_macaddr (&dev);
> - break;
> - default:
> - break;
> - }
> -
> - }
> -
> - return (0);
> -}
> -
> -void copy_from_eeprom (struct eth_device *dev)
> -{
> - int i;
> -
> - SMC_SELECT_BANK (dev, 1);
> - SMC_outw (dev, (SMC_inw (dev, CTL_REG) & !CTL_EEPROM_SELECT) |
> - CTL_RELOAD, CTL_REG);
> - i = 100;
> - while ((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --i)
> - udelay(100);
> - if (i == 0) {
> - printf ("Timeout Refreshing EEPROM registers\n");
> - } else {
> - printf ("EEPROM contents copied to MAC\n");
> - }
> -
> -}
> -
> -void print_macaddr (struct eth_device *dev)
> -{
> - int i, j, k, mac[6];
> -
> - printf ("Current MAC Address in SMSC91111 ");
> - SMC_SELECT_BANK (dev, 1);
> - for (i = 0; i < 5; i++) {
> - printf ("%02x:", SMC_inb (dev, ADDR0_REG + i));
> - }
> -
> - printf ("%02x\n", SMC_inb (dev, ADDR0_REG + 5));
> -
> - i = 0;
> - for (j = 0x20; j < 0x23; j++) {
> - k = read_eeprom_reg (dev, j);
> - mac[i] = k & 0xFF;
> - i++;
> - mac[i] = k >> 8;
> - i++;
> - }
> -
> - printf ("Current MAC Address in EEPROM ");
> - for (i = 0; i < 5; i++)
> - printf ("%02x:", mac[i]);
> - printf ("%02x\n", mac[5]);
> -
> -}
> -void dump_eeprom (struct eth_device *dev)
> -{
> - int j, k;
> -
> - printf ("IOS2-0 ");
> - for (j = 0; j < 8; j++) {
> - printf ("%03x ", j);
> - }
> - printf ("\n");
> -
> - for (k = 0; k < 4; k++) {
> - if (k == 0)
> - printf ("CONFIG ");
> - if (k == 1)
> - printf ("BASE ");
> - if ((k == 2) || (k == 3))
> - printf (" ");
> - for (j = 0; j < 0x20; j += 4) {
> - printf ("%02x:%04x ", j + k,
> - read_eeprom_reg (dev, j + k));
> - }
> - printf ("\n");
> - }
> -
> - for (j = 0x20; j < 0x40; j++) {
> - if ((j & 0x07) == 0)
> - printf ("\n");
> - printf ("%02x:%04x ", j, read_eeprom_reg (dev, j));
> - }
> - printf ("\n");
> -
> -}
> -
> -int read_eeprom_reg (struct eth_device *dev, int reg)
> -{
> - int timeout;
> -
> - SMC_SELECT_BANK (dev, 2);
> - SMC_outw (dev, reg, PTR_REG);
> -
> - SMC_SELECT_BANK (dev, 1);
> - SMC_outw (dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT |
> - CTL_RELOAD, CTL_REG);
> - timeout = 100;
> - while ((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout)
> - udelay(100);
> - if (timeout == 0) {
> - printf ("Timeout Reading EEPROM register %02x\n", reg);
> - return 0;
> - }
> -
> - return SMC_inw (dev, GP_REG);
> -
> -}
> -
> -int write_eeprom_reg (struct eth_device *dev, int value, int reg)
> -{
> - int timeout;
> -
> - SMC_SELECT_BANK (dev, 2);
> - SMC_outw (dev, reg, PTR_REG);
> -
> - SMC_SELECT_BANK (dev, 1);
> - SMC_outw (dev, value, GP_REG);
> - SMC_outw (dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT |
> - CTL_STORE, CTL_REG);
> - timeout = 100;
> - while ((SMC_inw (dev, CTL_REG) & CTL_STORE) && --timeout)
> - udelay(100);
> - if (timeout == 0) {
> - printf ("Timeout Writing EEPROM register %02x\n", reg);
> - return 0;
> - }
> -
> - return 1;
> -
> -}
> -
> -void dump_reg (struct eth_device *dev)
> -{
> - int i, j;
> -
> - printf (" ");
> - for (j = 0; j < 4; j++) {
> - printf ("Bank%i ", j);
> - }
> - printf ("\n");
> - for (i = 0; i < 0xF; i += 2) {
> - printf ("%02x ", i);
> - for (j = 0; j < 4; j++) {
> - SMC_SELECT_BANK (dev, j);
> - printf ("%04x ", SMC_inw (dev, i));
> - }
> - printf ("\n");
> - }
> -}
> diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
> index 2752152f68ee..7b9a5b1c5415 100644
> --- a/include/configs/integratorcp.h
> +++ b/include/configs/integratorcp.h
> @@ -19,14 +19,6 @@
> /* Integrator CP-specific configuration */
> #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */
>
> -/*
> - * Hardware drivers
> - */
> -#define CONFIG_SMC91111
> -#define CONFIG_SMC_USE_32_BIT
> -#define CONFIG_SMC91111_BASE 0xC8000000
> -#undef CONFIG_SMC91111_EXT_PHY
> -
> #define CONFIG_SERVERIP 192.168.1.100
> #define CONFIG_IPADDR 192.168.1.104
>
> diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h
> index 077428f50040..0c11b6b3331e 100644
> --- a/include/configs/vexpress_aemv8.h
> +++ b/include/configs/vexpress_aemv8.h
> @@ -84,12 +84,6 @@
> #endif
> #endif /* !CONFIG_GICV3 */
>
> -#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && !defined(CONFIG_DM_ETH)
> -/* The Vexpress64 BASE_FVP simulator uses SMSC91C111 */
> -#define CONFIG_SMC91111 1
> -#define CONFIG_SMC91111_BASE (V2M_PA_BASE + 0x01A000000)
> -#endif
> -
> /* PL011 Serial Configuration */
> #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
> #define CONFIG_PL011_CLOCK 7372800
> --
> 2.25.1
>
Acked-by: Ramon Fried <rfried.dev at gmail.com>
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