[PATCH 22/31] clk: mediatek: add CLK_BYPASS_XTAL flag to allow bypassing searching clock parent of xtal clock

[Weijie Gao]

On Thu, 2022-08-04 at 07:57 -0600, Simon Glass wrote:
> Hi Weijie,
> 
> On Wed, 3 Aug 2022 at 21:39, Weijie Gao <weijie.gao at mediatek.com>
> wrote:
> > 
> > The mtk clock framework in u-boot uses array index for searching
> > clock
> > parent (kernel uses strings for search), so we need to specify a
> > special
> > clock with ID=0 for CLK_XTAL in u-boot.
> > 
> > In the mt7622/mt7629 clock tree, the clocks with ID=0 never call
> > mtk_topckgen_get_mux_rate, adn return xtal clock directly. This
> > what we
> > expected.
> > 
> > However for newer chips, they may have some clocks with ID=0 not
> > representing the xtal clock and still needs
> > mtk_topckgen_get_mux_rate be
> > called. Current logic will make entire clock driver not working.
> > 
> > This patch adds a flag to indicate that whether a clock driver
> > needs clocks
> > with ID=0 to call mtk_topckgen_get_mux_rate.
> > 
> > Signed-off-by: Weijie Gao <weijie.gao at mediatek.com>
> > ---
> >  drivers/clk/mediatek/clk-mtk.c | 5 ++++-
> >  drivers/clk/mediatek/clk-mtk.h | 3 +++
> >  2 files changed, 7 insertions(+), 1 deletion(-)
> 
> Reviewed-by: Simon Glass <sjg at chromium.org>
> 
> > 
> > diff --git a/drivers/clk/mediatek/clk-mtk.c
> > b/drivers/clk/mediatek/clk-mtk.c
> > index d43b8a0648..d99ea55df0 100644
> > --- a/drivers/clk/mediatek/clk-mtk.c
> > +++ b/drivers/clk/mediatek/clk-mtk.c
> > @@ -314,12 +314,15 @@ static ulong mtk_topckgen_get_mux_rate(struct
> > clk
> >  *clk, u32 off)
> >         struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
> >         const struct mtk_composite *mux = &priv->tree->muxes[off];
> >         u32 index;
> > +       u32 flag = 0;
> > 
> >         index = readl(priv->base + mux->mux_reg);
> >         index &= mux->mux_mask << mux->mux_shift;
> >         index = index >> mux->mux_shift;
> > 
> > -       if (mux->parent[index])
> > +       if (mux->parent[index] == CLK_XTAL && priv->tree->flags &
> > CLK_BYPASS_XTAL)
> > +               flag = 1;
> > +       if (mux->parent[index] > 0 || flag == 1)
> >                 return mtk_clk_find_parent_rate(clk, mux-
> > >parent[index],
> >                                                 NULL);
> > 
> > diff --git a/drivers/clk/mediatek/clk-mtk.h
> > b/drivers/clk/mediatek/clk-mtk.h
> > index 95a23d14a8..0ab6912bf0 100644
> > --- a/drivers/clk/mediatek/clk-mtk.h
> > +++ b/drivers/clk/mediatek/clk-mtk.h
> > @@ -11,6 +11,8 @@
> >  #define CLK_XTAL                       0
> >  #define MHZ                            (1000 * 1000)
> > 
> > +#define CLK_BYPASS_XTAL                        BIT(0)
> > +
> >  #define HAVE_RST_BAR                   BIT(0)
> >  #define CLK_DOMAIN_SCPSYS              BIT(0)
> >  #define CLK_MUX_SETCLR_UPD             BIT(1)
> > @@ -197,6 +199,7 @@ struct mtk_clk_tree {
> >         const struct mtk_fixed_clk *fclks;
> >         const struct mtk_fixed_factor *fdivs;
> >         const struct mtk_composite *muxes;
> > +       u32 flags;
> 
> This needs a comment as to what the flags mean

OK.

> 
> >  };
> > 
> >  struct mtk_clk_priv {
> > --
> > 2.17.1
> > 
> 
> Regards,
> Simon