[SPAM] rk3399 TPL memory setup code triggers clock frequency limit assertion

[Michal Suchánek]

On Mon, Aug 08, 2022 at 04:28:33PM +0200, Xavier Drudis Ferran wrote:
> El Sun, Aug 07, 2022 at 04:44:04PM +0200, Michal Suchánek deia:
> > Hello,
> > 
> > when compiled with clock debug rk3399 cannot be booted because memory
> > setup code triggers clock assertion:
> > 
> > U-Boot TPL 2022.07-00038-g61e11a8e9f-dirty (Aug 07 2022 - 16:13:17)
> > TPL PLL at ff760000: fbdiv=50, refdiv=1, postdiv1=2, postdiv2=1, vco=1200000 khz, output=600000 khz
> > TPL PLL at ff760020: fbdiv=50, refdiv=1, postdiv1=2, postdiv2=1, vco=1200000 khz, output=600000 khz
> > TPL PLL at ff760080: fbdiv=99, refdiv=2, postdiv1=2, postdiv2=1, vco=1188000 khz, output=594000 khz
> > TPL PLL at ff760060: fbdiv=64, refdiv=1, postdiv1=2, postdiv2=2, vco=1536000 khz, output=384000 khz
> > TPL PLL at ff760040: fbdiv=12, refdiv=1, postdiv1=3, postdiv2=2, vco=288000 khz, output=48000 khz
> > drivers/clk/rockchip/clk_rk3399.c:347: rkclk_set_pll: Assertion `vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX' failed.Channel 0: LPDDR4, 50MHz
> 
> Sorry, I don't have time now. But It might be related to 
> 
> https://patchwork.ozlabs.org/project/uboot/patch/20220716103144.GA2167@begut/
> 
> Apparently this clock is wrong but nobody finds any consequence of it being wrong. 
> If one asks for a 50MHz clock and gets a 48MHz clockthings might work anyway, but 
> it's nice that at least when one asks to be told of problems one is told.

Yes, that's exactly what I was looking for. It resolves the discrepancy
between the asssert and the set clock by adjusting the clock settings.

Thanks

Michal

U-Boot TPL 2022.07-00044-gc1e2523e7d-dirty (Aug 08 2022 - 18:10:27)
TPL PLL at ff760000: fbdiv=50, refdiv=1, postdiv1=2, postdiv2=1, vco=1200000 khz, output=600000 khz
TPL PLL at ff760020: fbdiv=50, refdiv=1, postdiv1=2, postdiv2=1, vco=1200000 khz, output=600000 khz
TPL PLL at ff760080: fbdiv=99, refdiv=2, postdiv1=2, postdiv2=1, vco=1188000 khz, output=594000 khz
TPL PLL at ff760060: fbdiv=64, refdiv=1, postdiv1=2, postdiv2=2, vco=1536000 khz, output=384000 khz
TPL PLL at ff760040: fbdiv=75, refdiv=2, postdiv1=3, postdiv2=6, vco=900000 khz, output=50000 khz
rk3399_clk_set_rate: clk clock-controller at ff760000 170 rate 50000000 -> 50000000
Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
256B stride
TPL PLL at ff760040: fbdiv=50, refdiv=1, postdiv1=3, postdiv2=1, vco=1200000 khz, output=400000 khz
rk3399_clk_set_rate: clk clock-controller at ff760000 170 rate 400000000 -> 400000000
lpddr4_set_rate: change freq to 400000000 mhz 0, 1
TPL PLL at ff760040: fbdiv=100, refdiv=1, postdiv1=3, postdiv2=1, vco=2400000 khz, output=800000 khz
rk3399_clk_set_rate: clk clock-controller at ff760000 170 rate 800000000 -> 800000000
lpddr4_set_rate: change freq to 800000000 mhz 1, 0
Trying to boot from BOOTROM
Returning to boot ROM...
SPL PLL at ff760000: fbdiv=50, refdiv=1, postdiv1=2, postdiv2=1, vco=1200000 khz, output=600000 khz
SPL PLL at ff760020: fbdiv=50, refdiv=1, postdiv1=2, postdiv2=1, vco=1200000 khz, output=600000 khz
SPL PLL at ff760080: fbdiv=99, refdiv=2, postdiv1=2, postdiv2=1, vco=1188000 khz, output=594000 khz
SPL PLL at ff760060: fbdiv=64, refdiv=1, postdiv1=2, postdiv2=2, vco=1536000 khz, output=384000 khz
rk3399_clk_get_rate: clk clock-controller at ff760000 83

U-Boot SPL 2022.07-00044-gc1e2523e7d-dirty (Aug 08 2022 - 18:10:27 +0200)