[PATCH 25/31] clk: mediatek: add CLK_XTAL support for clock driver

[Weijie Gao]

On Sat, 2022-08-13 at 00:25 -0400, Sean Anderson wrote:
> On 8/3/22 11:36 PM, Weijie Gao wrote:
> > This add CLK_XTAL macro and flag to mediatek clock driver common
> > part,
> > to make thi SoC that has clock directlly connect to XTAL working.
> 
> nit: this.. directly
> 
> But I'm having trouble reading your commit message. Perhaps something
> like
> 
> > This adds the CLK_XTAL macro/flag to allow modeling clocks which
> > are
> > directly connected to a fixed-rate clock.

Oh. I've put wrong commit description here.

> > 
> > Signed-off-by: Weijie Gao <weijie.gao at mediatek.com>
> > ---
> >   drivers/clk/mediatek/clk-mtk.c | 3 +++
> >   drivers/clk/mediatek/clk-mtk.h | 3 ++-
> >   2 files changed, 5 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/clk/mediatek/clk-mtk.c
> > b/drivers/clk/mediatek/clk-mtk.c
> > index be3846c85b..5a4650d137 100644
> > --- a/drivers/clk/mediatek/clk-mtk.c
> > +++ b/drivers/clk/mediatek/clk-mtk.c
> > @@ -296,6 +296,7 @@ static ulong
> > mtk_topckgen_get_factor_rate(struct clk
> >   *clk, u32 off)
> >   		rate = mtk_clk_find_parent_rate(clk, fdiv-
> > >parent, NULL);
> >   		break;
> >   
> > +	case CLK_PARENT_XTAL:
> >   	default:
> >   		rate = priv->tree->xtal_rate;
> >   	}
> > @@ -314,6 +315,8 @@ static ulong
> > mtk_infrasys_get_factor_rate(struct clk
> >   *clk, u32 off)
> >   		rate = mtk_clk_find_parent_rate(clk, fdiv-
> > >parent,
> >   						priv->parent);
> >   		break;
> > +	case CLK_PARENT_XTAL:
> > +		rate = priv->tree->xtal_rate;
> >   	default:
> >   		rate = mtk_clk_find_parent_rate(clk, fdiv-
> > >parent, NULL);
> >   	}
> > diff --git a/drivers/clk/mediatek/clk-mtk.h
> > b/drivers/clk/mediatek/clk-mtk.h
> > index 8536275671..211356697b 100644
> > --- a/drivers/clk/mediatek/clk-mtk.h
> > +++ b/drivers/clk/mediatek/clk-mtk.h
> > @@ -26,7 +26,8 @@
> >   #define CLK_PARENT_APMIXED		BIT(4)
> >   #define CLK_PARENT_TOPCKGEN		BIT(5)
> >   #define CLK_PARENT_INFRASYS		BIT(6)
> > -#define CLK_PARENT_MASK			GENMASK(6, 4)
> > +#define CLK_PARENT_XTAL			BIT(7)
> > +#define CLK_PARENT_MASK			GENMASK(7, 4)
> >   
> >   #define ETHSYS_HIFSYS_RST_CTRL_OFS	0x34
> >   
> > 
> 
>