[PATCH v4 3/3] ARM: imx6: dh-imx6: Enable d-cache early in SPL

[Philip Oberfichtner]

Hi,

thanks for the feedback.

On Wed, 2022-08-17 at 11:24 +0200, Marek Vasut wrote:
> On 8/17/22 11:06, Philip Oberfichtner wrote:
> 
> [...]
> 
> > +void spl_board_prepare_for_boot(void)
> > +{
> > +       /*
> > +        * Flush dcache.
> 
> The dcache_disable() does not do any cache flushing, it just disables
> the Dcache enable C-bit.

See the following objdump jumping to flush_dcache_all(). The
implementation of dcache_disable() is in arch/arm/lib/cache-cp15.c.

$ ${CROSS_COMPILE}objdump spl/u-boot-spl --disassemble=dcache_disable
                                                                                             
spl/u-boot-spl:     file format elf32-littlearm                       
                                                                                             
                                                                                             
Disassembly of section .text:                                         
                                                                                             
0090b498 <dcache_disable>:                                            
  90b498:       b510            push    {r4, lr}                      
  90b49a:       ee11 3f10       mrc     15, 0, r3, cr1, cr0, {0}      
  90b49e:       075b            lsls    r3, r3, #29                   
  90b4a0:       d509            bpl.n   90b4b6 <dcache_disable+0x1e>  
  90b4a2:       ee11 4f10       mrc     15, 0, r4, cr1, cr0, {0}      
  90b4a6:       f7ff fbfb       bl      90aca0 <flush_dcache_all>     
  90b4aa:       f024 0405       bic.w   r4, r4, #5                    
  90b4ae:       ee01 4f10       mcr     15, 0, r4, cr1, cr0, {0}      
  90b4b2:       f3bf 8f6f       isb     sy                            
  90b4b6:       bd10            pop     {r4, pc}                      
$              

I'll add a note to the comment about flush_dcache_all() being called. 


> 
> > Without it U-Boot proper would hang at random locations. Presumably
> > this is
> > +        * due to dirty cache lines remaining after SPL passes
> > control. When U-Boot proper later on
> > +        * calls invalidate_dcache_all(), those dirty cache lines
> > will get lost.
> > +        */
> 
> What about falcon boot mode starting Linux from SPL, could it fail
> the 
> same way ?

Yes, assuming my dirty-cache-line hypothesis is correct. I'll
generalize the comment in V5.

> 
> > +       dcache_disable();
> > +}
> 
> [...]