[PATCH v5 1/3] Convert CONFIG_SYS_L2_PL310 to Kconfig

Philip Oberfichtner pro at denx.de
Wed Aug 17 13:02:44 CEST 2022 

This converts CONFIG_SYS_L2_PL310 to Kconfig.

For omap2 and mvebu the 'select SYS_L2_PL310' locations were
determined using ./tools/moveconfig -i CONFIG_SYS_L2_PL310.

For mx6 I manually chose ARCH_MX6 as 'select' location. The
correctness has been verified using

	$ ./tools/moveconfig.py -f ARCH_MX6 ~SYS_L2_PL310 ~SYS_L2CACHE_OFF
	0 matches

That means whenever an ARCH_MX6 board had SYS_L2_PL310 disabled, this
was correctly reflected in SYS_L2CACHE_OFF. Thus it's safe to insert
the 'select' statement under ARCH_MX6.

Signed-off-by: Philip Oberfichtner <pro at denx.de>
---
I wonder if we could further reduce the diffstat by using 'select' for
all the socfpga boards. I did not find an appropriate way - I'm open for
suggestions, though.

(no changes since v4)

Changes in v4:
        - Reduce diffstat by using 'select' statements for omap2, mvebu
          and mx6 based boards

Changes in v3:
        new

 README                                    | 2 --
 arch/arm/Kconfig                          | 5 +++++
 arch/arm/mach-mvebu/Kconfig               | 1 +
 arch/arm/mach-mvebu/include/mach/config.h | 2 --
 arch/arm/mach-omap2/Kconfig               | 1 +
 configs/omap4_panda_defconfig             | 1 +
 configs/omap4_sdp4430_defconfig           | 1 +
 configs/poleg_evb_defconfig               | 1 +
 configs/socfpga_arria10_defconfig         | 1 +
 configs/socfpga_arria5_defconfig          | 1 +
 configs/socfpga_chameleonv3_defconfig     | 1 +
 configs/socfpga_cyclone5_defconfig        | 1 +
 configs/socfpga_dbm_soc1_defconfig        | 1 +
 configs/socfpga_de0_nano_soc_defconfig    | 1 +
 configs/socfpga_de10_nano_defconfig       | 1 +
 configs/socfpga_de10_standard_defconfig   | 1 +
 configs/socfpga_de1_soc_defconfig         | 1 +
 configs/socfpga_is1_defconfig             | 1 +
 configs/socfpga_mcvevk_defconfig          | 1 +
 configs/socfpga_secu1_defconfig           | 1 +
 configs/socfpga_sockit_defconfig          | 1 +
 configs/socfpga_socrates_defconfig        | 1 +
 configs/socfpga_sr1500_defconfig          | 1 +
 configs/socfpga_vining_fpga_defconfig     | 1 +
 configs/stemmy_defconfig                  | 1 +
 include/configs/am43xx_evm.h              | 1 -
 include/configs/brppt2.h                  | 1 -
 include/configs/cm_t43.h                  | 1 -
 include/configs/mx6_common.h              | 1 -
 include/configs/odroid.h                  | 1 -
 include/configs/poleg.h                   | 1 -
 include/configs/socfpga_common.h          | 1 -
 include/configs/stemmy.h                  | 1 -
 include/configs/ti_omap4_common.h         | 1 -
 include/configs/trats.h                   | 1 -
 include/configs/trats2.h                  | 1 -
 include/configs/zynq-common.h             | 1 -
 scripts/config_whitelist.txt              | 1 -
 38 files changed, 27 insertions(+), 17 deletions(-)

diff --git a/README b/README
index 6b6f722733..595f007aaf 100644
--- a/README
+++ b/README
@@ -496,8 +496,6 @@ The following options need to be configured:
 		the defaults discussed just above.
 
 - Cache Configuration for ARM:
-		CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache
-				      controller
 		CONFIG_SYS_PL310_BASE - Physical base address of PL310
 					controller register space
 
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 949ebb46ba..b094d2d51f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -488,6 +488,10 @@ config TPL_SYS_THUMB_BUILD
 	   density. For ARM architectures that support Thumb2 this flag will
 	   result in Thumb2 code generated by GCC.
 
+config SYS_L2_PL310
+	bool "ARM PL310 L2 cache controller"
+	help
+	  Enable support for ARM PL310 L2 cache controller in U-Boot
 
 config SYS_L2CACHE_OFF
 	bool "L2cache off"
@@ -989,6 +993,7 @@ config ARCH_MX6
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
+	select SYS_L2_PL310 if !SYS_L2CACHE_OFF
 	imply MXC_GPIO
 	imply SYS_THUMB_BUILD
 	imply SPL_SEPARATE_BSS
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index a81b8e2b0d..2ebe341ed1 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -14,6 +14,7 @@ config ARMADA_32BIT
 	select SPL_SKIP_LOWLEVEL_INIT if SPL
 	select SPL_SIMPLE_BUS if SPL
 	select SUPPORT_SPL
+	select SYS_L2_PL310 if !SYS_L2CACHE_OFF
 	select TRANSLATION_OFFSET
 	select SPL_SYS_NO_VECTOR_TABLE if SPL
 	select ARCH_VERY_EARLY_INIT
diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h
index 4add0d9e10..0bba0a4cf9 100644
--- a/arch/arm/mach-mvebu/include/mach/config.h
+++ b/arch/arm/mach-mvebu/include/mach/config.h
@@ -25,8 +25,6 @@
 #define MV88F78X60 /* for the DDR training bin_hdr code */
 #endif
 
-#define CONFIG_SYS_L2_PL310
-
 #define MV_UART_CONSOLE_BASE		MVEBU_UART0_BASE
 
 /* Needed for SPI NOR booting in SPL */
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index fa41047476..fee437c4dc 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -96,6 +96,7 @@ config TI816X
 config AM43XX
 	bool "AM43XX SoC"
 	select SPECIFY_CONSOLE_INDEX
+	select SYS_L2_PL310 if !SYS_L2CACHE_OFF
 	imply NAND_OMAP_ELM
 	imply NAND_OMAP_GPMC
 	imply SPL_DM
diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig
index bd6c2ce4ca..899ba50a16 100644
--- a/configs/omap4_panda_defconfig
+++ b/configs/omap4_panda_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_DEFAULT_DEVICE_TREE="omap4-panda"
diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig
index 62eb75d1f9..82cfc4ab1a 100644
--- a/configs/omap4_sdp4430_defconfig
+++ b/configs/omap4_sdp4430_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
 # CONFIG_SPL_USE_ARCH_MEMSET is not set
 CONFIG_ARCH_OMAP2PLUS=y
diff --git a/configs/poleg_evb_defconfig b/configs/poleg_evb_defconfig
index 16f6215148..4669c7fe86 100644
--- a/configs/poleg_evb_defconfig
+++ b/configs/poleg_evb_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_CPU_INIT=y
+CONFIG_SYS_L2_PL310=y
 CONFIG_ARCH_NPCM=y
 CONFIG_SYS_TEXT_BASE=0x8200
 CONFIG_SYS_MALLOC_LEN=0x240000
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index c98c106851..716a68a67b 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_ENV_SIZE=0x2000
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 24c21090b1..810604ec03 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_ENV_SIZE=0x2000
diff --git a/configs/socfpga_chameleonv3_defconfig b/configs/socfpga_chameleonv3_defconfig
index e78d3b51de..80a965c7e2 100644
--- a/configs/socfpga_chameleonv3_defconfig
+++ b/configs/socfpga_chameleonv3_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x4400
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index d010b54240..7383fa1d3e 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_ENV_SIZE=0x2000
diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig
index a1574b6a5d..9f1bed2b75 100644
--- a/configs/socfpga_dbm_soc1_defconfig
+++ b/configs/socfpga_dbm_soc1_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_ENV_SIZE=0x2000
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index ec7355d2cc..8e4154f46c 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_ENV_SIZE=0x2000
diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig
index b62f029962..713048ab3a 100644
--- a/configs/socfpga_de10_nano_defconfig
+++ b/configs/socfpga_de10_nano_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_ENV_SIZE=0x2000
diff --git a/configs/socfpga_de10_standard_defconfig b/configs/socfpga_de10_standard_defconfig
index b8bc9da4d0..67b2bafbe8 100644
--- a/configs/socfpga_de10_standard_defconfig
+++ b/configs/socfpga_de10_standard_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_ENV_SIZE=0x2000
diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig
index 749ec540b4..8bae98e130 100644
--- a/configs/socfpga_de1_soc_defconfig
+++ b/configs/socfpga_de1_soc_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_ENV_SIZE=0x2000
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index 958adfe25a..b7735689bc 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_ENV_SIZE=0x2000
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index 18e125f5bd..0e47bcd4e7 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_ENV_SIZE=0x2000
diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig
index 83e24402a8..89df845ad7 100644
--- a/configs/socfpga_secu1_defconfig
+++ b/configs/socfpga_secu1_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_SYS_MALLOC_F_LEN=0x800
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 2a02f1dbfa..c16b3e4820 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_ENV_SIZE=0x2000
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 3d0c48d766..7bcea6726b 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_ENV_SIZE=0x2000
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index def2ee8dbc..55388da88c 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_ENV_SIZE=0x4000
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index d0c87416ef..9c89d631f5 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_ENV_SIZE=0x4000
diff --git a/configs/stemmy_defconfig b/configs/stemmy_defconfig
index 7fc0a39872..f1d3ef5b12 100644
--- a/configs/stemmy_defconfig
+++ b/configs/stemmy_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_L2_PL310=y
 CONFIG_ARCH_U8500=y
 CONFIG_SUPPORT_PASSING_ATAGS=y
 # CONFIG_SETUP_MEMORY_TAGS is not set
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 87d3a27099..fc82a8c003 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -29,7 +29,6 @@
 /* SPL defines. */
 
 /* Enabling L2 Cache */
-#define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE	0x48242000
 
 /*
diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h
index adaba410ce..0c7fe5f3ab 100644
--- a/include/configs/brppt2.h
+++ b/include/configs/brppt2.h
@@ -13,7 +13,6 @@
 
 /* -- i.mx6 specifica -- */
 #ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE		L2_PL310_BASE
 #endif /* !CONFIG_SYS_L2CACHE_OFF */
 
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index 07c5cb8ded..50cb2a4718 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -36,7 +36,6 @@
 #define CONFIG_POWER_TPS65218
 
 /* Enabling L2 Cache */
-#define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE		0x48242000
 
 /*
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index e416f81e43..4314556754 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -12,7 +12,6 @@
 #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
 #else
 #ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE	L2_PL310_BASE
 #endif
 
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index 7448cc9520..babd3ca963 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -14,7 +14,6 @@
 #include <configs/exynos4-common.h>
 
 #ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE	0x10502000
 #endif
 
diff --git a/include/configs/poleg.h b/include/configs/poleg.h
index f1c259f476..05253d59ef 100644
--- a/include/configs/poleg.h
+++ b/include/configs/poleg.h
@@ -7,7 +7,6 @@
 #define __CONFIG_POLEG_H
 
 #ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_L2_PL310		1
 #define CONFIG_SYS_PL310_BASE	0xF03FC000       /* L2 - Cache Regs Base (4k Space)*/
 #endif
 
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 4a7da76e51..c3f30afe2b 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -48,7 +48,6 @@
 /*
  * Cache
  */
-#define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS
 
 /*
diff --git a/include/configs/stemmy.h b/include/configs/stemmy.h
index 71b25c23b1..3c70856fc7 100644
--- a/include/configs/stemmy.h
+++ b/include/configs/stemmy.h
@@ -15,7 +15,6 @@
  */
 
 /* FIXME: This should be loaded from device tree... */
-#define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE		0xa0412000
 
 /* Linux does not boot if FDT / initrd is loaded to end of RAM */
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
index 3d78972bfe..0568946fc8 100644
--- a/include/configs/ti_omap4_common.h
+++ b/include/configs/ti_omap4_common.h
@@ -12,7 +12,6 @@
 #define __CONFIG_TI_OMAP4_COMMON_H
 
 #ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_L2_PL310		1
 #define CONFIG_SYS_PL310_BASE	0x48242000
 #endif
 
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 53f5a6996b..530b413d5b 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -12,7 +12,6 @@
 #include <configs/exynos4-common.h>
 
 #ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE	0x10502000
 #endif
 
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index b7449dab8b..06c1fcd23e 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -13,7 +13,6 @@
 #include <configs/exynos4-common.h>
 
 #ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE	0x10502000
 #endif
 
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 75ae68766f..dc0cba0010 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -11,7 +11,6 @@
 
 /* Cache options */
 #ifndef CONFIG_SYS_L2CACHE_OFF
-# define CONFIG_SYS_L2_PL310
 # define CONFIG_SYS_PL310_BASE		0xf8f02000
 #endif
 
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 4f628e0f10..d9d24c0ae0 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -908,7 +908,6 @@ CONFIG_SYS_JFFS2_FIRST_SECTOR
 CONFIG_SYS_JFFS2_NUM_BANKS
 CONFIG_SYS_KMBEC_FPGA_BASE
 CONFIG_SYS_KMBEC_FPGA_SIZE
-CONFIG_SYS_L2_PL310
 CONFIG_SYS_L2_SIZE
 CONFIG_SYS_L3_SIZE
 CONFIG_SYS_LATCH_ADDR
-- 
2.37.1

More information about the U-Boot mailing list