[PATCH] powerpc: remove support for kmtergr1 and MPC8309

Holger Brunck holger.brunck at hitachienergy.com
Fri Aug 19 16:55:06 CEST 2022


The kmtegr1 board is out of maintenance and can be removed. As it is the
only board in the tree using MPC8309 the support for this CPU is dropped
completely.

Signed-off-by: Holger Brunck <holger.brunck at hitachienergy.com>
---
 arch/powerpc/cpu/mpc83xx/Kconfig              |   9 -
 arch/powerpc/cpu/mpc83xx/hrcw/Kconfig         |  18 -
 arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr |   2 +-
 arch/powerpc/cpu/mpc83xx/speed.c              |  17 -
 arch/powerpc/dts/km8309-uboot.dtsi            |  33 --
 arch/powerpc/dts/kmtegr1.dts                  | 392 ------------------
 arch/powerpc/include/asm/arch-mpc83xx/gpio.h  |   3 +-
 arch/powerpc/include/asm/global_data.h        |   2 -
 arch/powerpc/include/asm/immap_83xx.h         |  60 ---
 arch/powerpc/include/asm/mpc8xxx_spi.h        |   1 -
 board/keymile/km83xx/Kconfig                  |  19 -
 board/keymile/km83xx/MAINTAINERS              |   3 -
 configs/kmtegr1_defconfig                     | 201 ---------
 drivers/qe/qe.c                               |   2 -
 include/configs/km/km-mpc8309.h               | 119 ------
 include/configs/kmtegr1.h                     |  58 ---
 include/linux/immap_qe.h                      |   2 +-
 include/mpc83xx.h                             | 151 -------
 18 files changed, 3 insertions(+), 1089 deletions(-)
 delete mode 100644 arch/powerpc/dts/km8309-uboot.dtsi
 delete mode 100644 arch/powerpc/dts/kmtegr1.dts
 delete mode 100644 configs/kmtegr1_defconfig
 delete mode 100644 include/configs/km/km-mpc8309.h
 delete mode 100644 include/configs/kmtegr1.h

diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 9d24f029b3..ec3405e967 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -132,15 +132,6 @@ config ARCH_MPC8308
 	select MPC83XX_PCIE1_SUPPORT
 	select MPC83XX_SECOND_I2C
 
-config ARCH_MPC8309
-	bool
-	select ARCH_MPC830X
-	select MPC83XX_QUICC_ENGINE
-	select MPC83XX_PCI_SUPPORT
-	select MPC83XX_SECOND_I2C
-	select SYS_FSL_ERRATUM_ESDHC111
-	select FSL_ELBC
-
 config ARCH_MPC831X
 	bool
 	select MPC83XX_PCI_SUPPORT
diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
index 71fa73801a..b67ccd661d 100644
--- a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
@@ -160,10 +160,6 @@ config QUICC_VCO_DIVIDER_2
 config QUICC_VCO_DIVIDER_4
 	bool "4"
 
-config QUICC_VCO_DIVIDER_8
-	depends on ARCH_MPC8309
-	bool "8"
-
 endchoice
 
 choice
@@ -399,14 +395,6 @@ config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
 	depends on ARCH_MPC837X
 	bool "PCI2"
 
-config BOOT_ROM_INTERFACE_ESDHC
-	depends on ARCH_MPC8309
-	bool "eSDHC"
-
-config BOOT_ROM_INTERFACE_SPI
-	depends on ARCH_MPC8309
-	bool "SPI"
-
 config BOOT_ROM_INTERFACE_GPCM_8BIT
 	bool "Local bus GPCM - 8-bit ROM"
 
@@ -623,8 +611,6 @@ config BOOT_ROM_INTERFACE
 	hex
 	default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM
 	default 0x4 if BOOT_ROM_INTERFACE_PCI1
-	default 0x8 if BOOT_ROM_INTERFACE_ESDHC
-	default 0xc if BOOT_ROM_INTERFACE_SPI
 	default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
 	default 0x14 if BOOT_ROM_INTERFACE_GPCM_8BIT
 	default 0x18 if BOOT_ROM_INTERFACE_GPCM_16BIT
@@ -676,12 +662,8 @@ config LDP_PIN_MUX_STATE
 config QUICC_VCO_DIVIDER
 	int
 	default 0 if !MPC83XX_QUICC_ENGINE
-	default 0 if QUICC_VCO_DIVIDER_2 && ARCH_MPC8309
-	default 1 if QUICC_VCO_DIVIDER_4 && ARCH_MPC8309
-	default 2 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8309
 	default 2 if QUICC_VCO_DIVIDER_2 && (ARCH_MPC832X || ARCH_MPC8360)
 	default 0 if QUICC_VCO_DIVIDER_4 && (ARCH_MPC832X || ARCH_MPC8360)
-	default 1 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8360
 
 config QUICC_DIV_FACTOR
 	int
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
index e6b6130de2..86c5f42dd3 100644
--- a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
+++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
@@ -1,6 +1,6 @@
 menu "LCRR - Clock Ratio Register register"
 
-if !ARCH_MPC8309 && !ARCH_MPC831X && !ARCH_MPC832X
+if !ARCH_MPC831X && !ARCH_MPC832X
 
 choice
 	prompt "DLL bypass"
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index f835263f25..b7a87fec2f 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -93,8 +93,6 @@ int get_clocks(void)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
 	u32 usbdr_clk;
-#elif defined(CONFIG_ARCH_MPC8309)
-	u32 usbdr_clk;
 #endif
 #ifdef CONFIG_ARCH_MPC834X
 	u32 usbmph_clk;
@@ -107,9 +105,7 @@ int get_clocks(void)
 #if defined(CONFIG_FSL_ESDHC)
 	u32 sdhc_clk;
 #endif
-#if !defined(CONFIG_ARCH_MPC8309)
 	u32 enc_clk;
-#endif
 	u32 lbiu_clk;
 	u32 lclk_clk;
 	u32 mem_clk;
@@ -252,7 +248,6 @@ int get_clocks(void)
 		return -6;
 	}
 #endif
-#if !defined(CONFIG_ARCH_MPC8309)
 	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
 	case 0:
 		enc_clk = 0;
@@ -270,7 +265,6 @@ int get_clocks(void)
 		/* unknown SCCR_ENCCM value */
 		return -7;
 	}
-#endif
 
 #if defined(CONFIG_FSL_ESDHC)
 	switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
@@ -304,8 +298,6 @@ int get_clocks(void)
 	i2c1_clk = sdhc_clk;
 #elif defined(CONFIG_ARCH_MPC837X)
 	i2c1_clk = enc_clk;
-#elif defined(CONFIG_ARCH_MPC8309)
-	i2c1_clk = csb_clk;
 #endif
 #if !defined(CONFIG_ARCH_MPC832X)
 	i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
@@ -434,8 +426,6 @@ int get_clocks(void)
 	gd->arch.tsec1_clk = tsec1_clk;
 	gd->arch.tsec2_clk = tsec2_clk;
 	gd->arch.usbdr_clk = usbdr_clk;
-#elif defined(CONFIG_ARCH_MPC8309)
-	gd->arch.usbdr_clk = usbdr_clk;
 #endif
 #if defined(CONFIG_ARCH_MPC834X)
 	gd->arch.usbmph_clk = usbmph_clk;
@@ -448,9 +438,7 @@ int get_clocks(void)
 #if !defined(CONFIG_ARCH_MPC832X)
 	gd->arch.i2c2_clk = i2c2_clk;
 #endif
-#if !defined(CONFIG_ARCH_MPC8309)
 	gd->arch.enc_clk = enc_clk;
-#endif
 	gd->arch.lbiu_clk = lbiu_clk;
 	gd->arch.lclk_clk = lclk_clk;
 	gd->mem_clk = mem_clk;
@@ -524,10 +512,8 @@ static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
 	printf("  DDR Secondary:       %-4s MHz\n",
 	       strmhz(buf, gd->arch.mem_sec_clk));
 #endif
-#if !defined(CONFIG_ARCH_MPC8309)
 	printf("  SEC:                 %-4s MHz\n",
 	       strmhz(buf, gd->arch.enc_clk));
-#endif
 	printf("  I2C1:                %-4s MHz\n",
 	       strmhz(buf, gd->arch.i2c1_clk));
 #if !defined(CONFIG_ARCH_MPC832X)
@@ -546,9 +532,6 @@ static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
 	       strmhz(buf, gd->arch.tsec2_clk));
 	printf("  USB DR:              %-4s MHz\n",
 	       strmhz(buf, gd->arch.usbdr_clk));
-#elif defined(CONFIG_ARCH_MPC8309)
-	printf("  USB DR:              %-4s MHz\n",
-	       strmhz(buf, gd->arch.usbdr_clk));
 #endif
 #if defined(CONFIG_ARCH_MPC834X)
 	printf("  USB MPH:             %-4s MHz\n",
diff --git a/arch/powerpc/dts/km8309-uboot.dtsi b/arch/powerpc/dts/km8309-uboot.dtsi
deleted file mode 100644
index a93bdb2d00..0000000000
--- a/arch/powerpc/dts/km8309-uboot.dtsi
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Hitachi Power Grids 8309 U-Boot specific Device Tree Source parts
- *
- * Copyright (C) 2020 Heiko Schocher <hs at denx.de>
- *
- */
-
-/ {
-	cpus {
-		u-boot,dm-pre-reloc;
-		PowerPC,8309 at 0 {
-			u-boot,dm-pre-reloc;
-		};
-	};
-
-	chosen {
-		stdout-path = &serial0;
-	};
-};
-
-&qe {
-	compatible = "fsl,qe", "simple-bus";
-};
-
-&soc {
-	u-boot,dm-pre-reloc;
-};
-
-&serial0 {
-	clock-frequency = <132000000>;
-	u-boot,dm-pre-reloc;
-};
diff --git a/arch/powerpc/dts/kmtegr1.dts b/arch/powerpc/dts/kmtegr1.dts
deleted file mode 100644
index d40d9716e5..0000000000
--- a/arch/powerpc/dts/kmtegr1.dts
+++ /dev/null
@@ -1,392 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Hitachi Power Grids TEGR1 Device Tree Source
- *
- * Copyright (C) 2020 Heiko Schocher <hs at denx.de>
- *
- */
-
-/dts-v1/;
-
-/ {
-	model = "KMTEGR1";
-	compatible = "hitachi,kmpbec8309";
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	aliases {
-		ethernet0 = &enet_zynq;
-		ethernet1 = &enet_piggy2;
-		serial0 = &serial0;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		PowerPC,8309 at 0 {
-			device_type = "cpu";
-			reg = <0x0>;
-			d-cache-line-size = <32>;	// 32 bytes
-			i-cache-line-size = <32>;	// 32 bytes
-			d-cache-size = <16384>;		// L1, 16K
-			i-cache-size = <16384>;		// L1, 16K
-			timebase-frequency = <66000000>;
-			bus-frequency = <264000000>;
-			clock-frequency = <264000000>;
-		};
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x00000000 0x10000000>;
-	};
-
-	soc: soc8309 at e0000000 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		device_type = "soc";
-		compatible = "simple-bus";
-		ranges = <0x0 0xe0000000 0x00100000>;
-		reg = <0xe0000000 0x00000200>;
-		bus-frequency = <264000000>;
-
-		i2c at 3000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			cell-index = <0>;
-			compatible = "fsl,mpc8313-i2c","fsl-i2c";
-			reg = <0x3000 0x100>;
-			interrupts = <14 0x8>;
-			interrupt-parent = <&ipic>;
-			clock-frequency = <400000>;
-
-			mux at 70 {
-				compatible = "nxp,pca9547";
-				reg = <0x70>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				i2c at 1 {
-					reg = <1>;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					/*
-					 * Inventory EEPROM of the
-					 * unit itself
-					 */
-					ivm at 50 {
-						label = "MAIN_CTRL";
-						compatible = "dummy";
-						reg = <0x50>;
-					};
-				};
-
-				i2c at 2 {
-					reg = <2>;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					/* Temperature sensors */
-					temp at 48 {
-						label = "front";
-						compatible = "national,lm75";
-						reg = <0x48>;
-					};
-
-					temp at 49 {
-						label = "board";
-						compatible = "national,lm75";
-						reg = <0x49>;
-					};
-
-					temp at 4a {
-						label = "power";
-						compatible = "national,lm75";
-						reg = <0x4a>;
-					};
-
-					temp at 4b {
-						label = "bottom";
-						compatible = "national,lm75";
-						reg = <0x4b>;
-					};
-				};
-
-				i2c at 6 {
-					reg = <6>;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-				};
-
-				i2c at 5 {
-					reg = <5>;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-				};
-
-				i2c at 7 {
-					reg = <7>;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-				};
-
-				i2c at 3 {
-					reg = <3>;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-				};
-			};
-		};
-
-		serial0: serial at 4500 {
-			cell-index = <0>;
-			device_type = "serial";
-			compatible = "fsl,ns16550", "ns16550";
-			reg = <0x4500 0x100>;
-			clock-frequency = <264000000>;
-			interrupts = <9 0x8>;
-			interrupt-parent = <&ipic>;
-		};
-
-		dma at 82a8 {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "fsl,mpc8309-dma", "fsl,elo-dma";
-			reg = <0x82a8 4>;
-			ranges = <0 0x8100 0x1a8>;
-			interrupt-parent = <&ipic>;
-			interrupts = <71 8>;
-			cell-index = <0>;
-			dma-channel at 0 {
-				compatible = "fsl,mpc8309-dma-channel",
-						"fsl,elo-dma-channel";
-				reg = <0 0x80>;
-				interrupt-parent = <&ipic>;
-				interrupts = <71 8>;
-			};
-			dma-channel at 80 {
-				compatible = "fsl,mpc8309-dma-channel",
-						"fsl,elo-dma-channel";
-				reg = <0x80 0x80>;
-				interrupt-parent = <&ipic>;
-				interrupts = <71 8>;
-			};
-			dma-channel at 100 {
-				compatible = "fsl,mpc8309-dma-channel",
-						"fsl,elo-dma-channel";
-				reg = <0x100 0x80>;
-				interrupt-parent = <&ipic>;
-				interrupts = <71 8>;
-			};
-			dma-channel at 180 {
-				compatible = "fsl,mpc8309-dma-channel",
-						"fsl,elo-dma-channel";
-				reg = <0x180 0x28>;
-				interrupt-parent = <&ipic>;
-				interrupts = <71 8>;
-			};
-		};
-
-		ipic: pic at 700 {
-			#address-cells = <0>;
-			#interrupt-cells = <2>;
-			compatible = "fsl,pq2pro-pic", "fsl,ipic";
-			interrupt-controller;
-			reg = <0x700 0x100>;
-			device_type = "ipic";
-		};
-
-		gpio1: gpio-controller at c00 {
-			#gpio-cells = <2>;
-			compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio";
-			reg = <0xc00 0x100>;
-			interrupts = <75 0x8>;
-			interrupt-parent = <&ipic>;
-			gpio-controller;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio2: gpio-controller at d00 {
-			#gpio-cells = <2>;
-			compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio";
-			reg = <0xd00 0x100>;
-			interrupts = <75 0x8>;
-			interrupt-parent = <&ipic>;
-			gpio-controller;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		spi at 7000 {
-			cell-index = <0>;
-			compatible = "fsl,spi";
-			reg = <0x7000 0x1000>;
-			interrupts = <16 0x8>;
-			interrupt-parent = <&ipic>;
-			mode = "cpu";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* GPIO_15 chipselect for ZYNQ flash */
-			gpios = <&gpio1 15 0>;
-
-			zynq_flash at 0 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				compatible = "spansion,m25p80";
-				reg = <0>;
-				spi-max-frequency = <4000000>;
-				m25p,fast-read;
-				partition at 0 {
-					label = "bootloader";
-					reg = <0x0 0x01000000>;
-				};
-			};
-		};
-	};
-
-	qe: qe at e0100000 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		device_type = "qe";
-		compatible = "fsl,qe";
-		ranges = <0x0 0xe0100000 0x00100000>;
-		reg = <0xe0100000 0x480>;
-		brg-frequency = <0>;
-		bus-frequency = <396000000>;
-		fsl,qe-num-snums = <32>;
-
-		muram at 10000 {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "fsl,qe-muram", "fsl,cpm-muram";
-			ranges = <0x0 0x00010000 0x00004000>;
-
-			data-only at 0 {
-				compatible = "fsl,qe-muram-data",
-					     "fsl,cpm-muram-data";
-				reg = <0x0 0x4000>;
-			};
-		};
-
-		/* ZYNQ (UCC1, MDIO 0x10, MII) */
-		enet_zynq: ethernet at 2000 {
-			device_type = "network";
-			compatible = "ucc_geth";
-			cell-index = <1>;
-			reg = <0x2000 0x200>;
-			interrupts = <32>;
-			interrupt-parent = <&qeic>;
-			local-mac-address = [ 00 00 00 00 00 00 ];
-			/*id=0, full-dup, 100M, no-pause, no-asym_p*/
-			fixed-link = <0 1 100 0 0>;
-			rx-clock-name = "clk9";
-			tx-clock-name = "clk10";
-			phy-connection-type = "mii";
-		};
-
-		/* Piggy2 (UCC3, MDIO 0x00, RMII) */
-		enet_piggy2: ucc at 2200 {
-			device_type = "network";
-			compatible = "ucc_geth";
-			cell-index = <3>;
-			reg = <0x2200 0x200>;
-			interrupts = <34>;
-			interrupt-parent = <&qeic>;
-			local-mac-address = [ 00 00 00 00 00 00 ];
-			rx-clock-name = "none";
-			tx-clock-name = "clk12";
-			phy-handle = <&phy_piggy2>;
-			phy-connection-type = "rmii";
-		};
-
-		mdio at 2320 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x2320 0x38>;
-			compatible = "fsl,ucc-mdio";
-
-			/* Piggy2 (UCC3, MDIO 0x00, RMII) */
-			phy_piggy2: ethernet-phy at 0 {
-				reg = <0x0>;
-				device_type = "ethernet-phy";
-			};
-
-			/* Explicitly set the tbi-phy to a non-zero address
-			 * so that it does not conflict with phy_piggy2 that
-			 * is unfortunately at address 0
-			 */
-			tbi1: tbi-phy at 1 {
-				reg = <0x1>;
-				device_type = "tbi-phy";
-			};
-		};
-
-		qeic: interrupt-controller at 80 {
-			interrupt-controller;
-			compatible = "fsl,qe-ic";
-			#address-cells = <0>;
-			#interrupt-cells = <1>;
-			reg = <0x80 0x80>;
-			big-endian;
-			interrupts = <32 8 33 8>;
-			interrupt-parent = <&ipic>;
-		};
-		bootcount at 0x13ff8 {
-			device_type = "bootcount";
-			compatible = "u-boot,bootcount";
-			reg = <0x13ff8 0x08>;
-		};
-
-	};
-	localbus at e0005000 {
-		#address-cells = <2>;
-		#size-cells = <1>;
-		compatible = "fsl,mpc8309-localbus", "fsl,pq2pro-localbus",
-			     "simple-bus";
-		reg = <0xe0005000 0xd8>;
-		ranges = <0 0 0xf0000000 0x04000000
-			1 0 0xe8000000 0x01000000
-			2 0 0xe0000000 0x10000000
-			3 0 0xb0000000 0x10000000>;
-
-		flash at 0,0 {
-			compatible = "cfi-flash";
-			reg = <0 0x00000000 0x04000000>;
-			bank-width = <2>;
-			nornand = "nor";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			use-advanced-sector-protection;
-			partition at 0 { /* 768KB */
-				label = "u-boot";
-				reg = <0 0xc0000>;
-			};
-			partition at c0000 { /* 256KB */
-				label = "qe-fw";
-				reg = <0xc0000 0x40000>;
-			};
-			partition at 100000 { /* 128KB */
-				label = "env";
-				reg = <0x100000 0x20000>;
-			};
-			partition at 120000 { /* 128KB */
-				label = "envred";
-				reg = <0x120000 0x20000>;
-			};
-			partition at 140000 { /* 64256KB */
-				label = "ubi0";
-				reg = <0x140000 0x3EC0000>;
-			};
-		};
-	};
-};
-
-#include "km8309-uboot.dtsi"
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
index b740675183..19c2506c9b 100644
--- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
@@ -8,8 +8,7 @@
  */
 #if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308)
 #define MPC83XX_GPIO_CTRLRS 1
-#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) || \
-	defined(CONFIG_ARCH_MPC8309)
+#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
 #define MPC83XX_GPIO_CTRLRS 2
 #else
 #define MPC83XX_GPIO_CTRLRS 0
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 770adcd30f..6709e692e6 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -32,8 +32,6 @@ struct arch_global_data {
 	u32 tsec1_clk;
 	u32 tsec2_clk;
 	u32 usbdr_clk;
-# elif defined(CONFIG_ARCH_MPC8309)
-	u32 usbdr_clk;
 # endif
 # if defined(CONFIG_ARCH_MPC834X)
 	u32 usbmph_clk;
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 6d1ddbcd27..c7313472de 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -64,14 +64,7 @@ typedef struct sysconf83xx {
 #else
 	u32 pecr2;		/* PCI Express control register 2 */
 #endif
-#if defined(CONFIG_ARCH_MPC8309)
-	u32 can_dbg_ctrl;
-	u32 res9a;
-	u32 gpr1;
-	u8 res9b[0xAC];
-#else
 	u8 res9[0xB8];
-#endif
 } sysconf83xx_t;
 
 /*
@@ -604,11 +597,7 @@ typedef struct serdes83xx {
  * On Chip ROM
  */
 typedef struct rom83xx {
-#if defined(CONFIG_ARCH_MPC8309)
-	u8 mem[0x8000];
-#else
 	u8 mem[0x10000];
-#endif
 } rom83xx_t;
 
 /*
@@ -857,55 +846,6 @@ typedef struct immap {
 	u8			res8[0xC0000];
 	u8			qe[0x100000];	/* QE block */
 } immap_t;
-#elif defined(CONFIG_ARCH_MPC8309)
-typedef struct immap {
-	sysconf83xx_t		sysconf;	/* System configuration */
-	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
-	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
-	rtclk83xx_t		pit;		/* Periodic Interval Timer */
-	gtm83xx_t		gtm[2];		/* Global Timers Module */
-	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
-	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
-	reset83xx_t		reset;		/* Reset Module */
-	clk83xx_t		clk;		/* System Clock Module */
-	pmc83xx_t		pmc;		/* Power Management Control Module */
-	gpio83xx_t		gpio[2];	/* General purpose I/O module */
-	u8			res0[0x500];	/* res0 1.25 KBytes added for 8309 */
-	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
-	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
-	u8			res1[0x800];
-	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
-	fsl_i2c_t		i2c[2];		/* I2C Controllers */
-	u8			res2[0x1300];
-	duart83xx_t		duart[2];	/* DUART */
-	u8			res3[0x200];
-	duart83xx_t		duart1[2];	/* DUART */
-	u8			res4[0x500];
-	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
-	u8			res5[0x1000];
-	spi8xxx_t		spi;		/* Serial Peripheral Interface */
-	dma83xx_t		dma;		/* DMA */
-	pciconf83xx_t		pci_conf[1];	/* PCI Configuration Registers */
-	u8			res7[0x80];
-	ios83xx_t		ios;		/* Sequencer (IOS) */
-	pcictrl83xx_t		pci_ctrl[1];	/* PCI Control & Status Registers */
-	u8			res8[0x13A00];
-	u8			can1[0x1000];	/* Flexcan 1 */
-	u8			can2[0x1000];	/* Flexcan 2 */
-	u8			res9[0x5000];
-	usb83xx_t		usb;
-	u8			res10[0x5000];
-	u8			can3[0x1000];	/* Flexcan 3 */
-	u8			can4[0x1000];	/* Flexcan 4 */
-	u8			res11[0x1000];
-	u8			dma1[0x2000];	/* DMA */
-	sdhc83xx_t		sdhc;		/* SDHC Controller */
-	u8			res12[0xC1000];
-	rom83xx_t		rom;		/* On Chip ROM */
-	u8			res13[0x8000];
-	u8			qe[0x100000];	/* QE block */
-	u8			res14[0xE00000];/* Added for 8309 */
-} immap_t;
 #endif
 
 struct ccsr_gpio {
diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h
index f2210a14ae..83cfe23b4e 100644
--- a/arch/powerpc/include/asm/mpc8xxx_spi.h
+++ b/arch/powerpc/include/asm/mpc8xxx_spi.h
@@ -11,7 +11,6 @@
 #include <asm/types.h>
 
 #if defined(CONFIG_ARCH_MPC8308) || \
-	defined(CONFIG_ARCH_MPC8309) || \
 	defined(CONFIG_ARCH_MPC8313) || \
 	defined(CONFIG_ARCH_MPC834X) || \
 	defined(CONFIG_ARCH_MPC837X)
diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig
index 8247ae39d3..ef3c62b9de 100644
--- a/board/keymile/km83xx/Kconfig
+++ b/board/keymile/km83xx/Kconfig
@@ -61,25 +61,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 
 endif
 
-if TARGET_KMTEGR1
-
-config SYS_BOARD
-	default "km83xx"
-
-config SYS_VENDOR
-	default "keymile"
-
-config SYS_CONFIG_NAME
-	default "kmtegr1"
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select ARCH_MPC8309
-	imply CMD_CRAMFS
-	imply FS_CRAMFS
-
-endif
-
 if TARGET_TUXX1
 
 config SYS_BOARD
diff --git a/board/keymile/km83xx/MAINTAINERS b/board/keymile/km83xx/MAINTAINERS
index 9fd5a8500d..ac1f8cbd88 100644
--- a/board/keymile/km83xx/MAINTAINERS
+++ b/board/keymile/km83xx/MAINTAINERS
@@ -10,10 +10,8 @@ F:	include/configs/tuxx1.h
 F:	configs/kmopti2_defconfig
 F:	configs/kmsupx5_defconfig
 F:	configs/kmtepr2_defconfig
-F:	configs/kmtegr1_defconfig
 F:	configs/tuge1_defconfig
 F:	configs/tuxx1_defconfig
-F:	arch/powerpc/dts/km8309-uboot.dtsi
 F:	arch/powerpc/dts/km8321-uboot.dtsi
 F:	arch/powerpc/dts/km8321.dtsi
 F:	arch/powerpc/dts/km836x-uboot.dtsi
@@ -25,7 +23,6 @@ F:	arch/powerpc/dts/kmeter1.dts
 F:	arch/powerpc/dts/kmopti2.dts
 F:	arch/powerpc/dts/kmsupc5.dts
 F:	arch/powerpc/dts/kmsupm5.dts
-F:	arch/powerpc/dts/kmtegr1.dts
 F:	arch/powerpc/dts/kmtepr2.dts
 F:	arch/powerpc/dts/kmtuge1.dts
 F:	arch/powerpc/dts/kmtuxa1.dts
diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig
deleted file mode 100644
index 7c0ebefa69..0000000000
--- a/configs/kmtegr1_defconfig
+++ /dev/null
@@ -1,201 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xF0000000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="kmtegr1"
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_ENV_ADDR=0xF0100000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_KMTEGR1=y
-CONFIG_SYSTEM_PLL_VCO_DIV_2=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_QUICC_MULT_FACTOR_3=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_INHIBITED=y
-CONFIG_BAT0_ICACHE_GUARDED=y
-CONFIG_BAT0_DCACHE_INHIBITED=y
-CONFIG_BAT0_DCACHE_GUARDED=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="IMMR"
-CONFIG_BAT1_BASE=0xE0000000
-CONFIG_BAT1_LENGTH_4_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
-CONFIG_BAT1_DCACHE_INHIBITED=y
-CONFIG_BAT1_DCACHE_GUARDED=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="KMBEC_FPGA"
-CONFIG_BAT2_BASE=0xE8000000
-CONFIG_BAT2_LENGTH_128_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="FLASH"
-CONFIG_BAT3_BASE=0xF0000000
-CONFIG_BAT3_LENGTH_256_MBYTES=y
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_DCACHE_INHIBITED=y
-CONFIG_BAT3_DCACHE_GUARDED=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT4=y
-CONFIG_BAT4_NAME="STACK_IN_DCACHE"
-CONFIG_BAT4_BASE=0xE6000000
-CONFIG_BAT4_ACCESS_RW=y
-CONFIG_BAT4_USER_MODE_VALID=y
-CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="APP2"
-CONFIG_BAT6_BASE=0xB0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_INHIBITED=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xF0000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_256_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xE8000000
-CONFIG_LBLAW1_NAME="KMBEC_FPGA"
-CONFIG_LBLAW1_LENGTH_128_MBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xB0000000
-CONFIG_LBLAW3_NAME="APP2"
-CONFIG_LBLAW3_LENGTH_256_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="APP2"
-CONFIG_BR3_OR3_BASE=0xB0000000
-CONFIG_BR3_PORTSIZE_16BIT=y
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_SCY_5=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_ACR_APARK_MASTER=y
-CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_2=y
-CONFIG_83XX_PCICLK=0x3ef1480
-CONFIG_KM_DEF_NETDEV="eth1"
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_LAST_STAGE_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
-CONFIG_SYS_BOOTM_LEN=0x2000000
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_DHCP=y
-CONFIG_BOOTP_BOOTFILESIZE=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=boot,nand0=app"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),256k(qe-fw),128k(env),128k(envred),-(ubi0);app:-(ubi1);"
-CONFIG_CMD_DIAG=y
-CONFIG_CMD_UBI=y
-# CONFIG_CMD_UBIFS is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR_REDUND=0xF0120000
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="UEC0"
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_DM_BOOTCOUNT=y
-CONFIG_BOOTCOUNT_MEM=y
-CONFIG_SYS_BOOTCOUNT_BE=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xF0001001
-CONFIG_SYS_OR0_PRELIM=0xF0000E55
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE8000801
-CONFIG_SYS_OR1_PRELIM=0xF8000E25
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xB0001001
-CONFIG_SYS_OR3_PRELIM=0xF0000050
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x3000
-CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
-CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
-CONFIG_SYS_I2C_SLAVE=0x7F
-CONFIG_SYS_I2C_SPEED=200000
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_FIXED=y
-CONFIG_DM_ETH_PHY=y
-CONFIG_QE_UEC=y
-# CONFIG_PCI is not set
-# CONFIG_PINCTRL_FULL is not set
-CONFIG_QE=y
-CONFIG_SYS_QE_FW_ADDR=0xF00C0000
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_BCH=y
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index bd0a10c9d2..8342c3389c 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -119,12 +119,10 @@ static void qe_sdma_init(void)
  */
 static u8 thread_snum[] = {
 /* Evthreads 16-29 are not supported in MPC8309 */
-#if !defined(CONFIG_ARCH_MPC8309)
 	0x04, 0x05, 0x0c, 0x0d,
 	0x14, 0x15, 0x1c, 0x1d,
 	0x24, 0x25, 0x2c, 0x2d,
 	0x34, 0x35,
-#endif
 	0x88, 0x89, 0x98, 0x99,
 	0xa8, 0xa9, 0xb8, 0xb9,
 	0xc8, 0xc9, 0xd8, 0xd9,
diff --git a/include/configs/km/km-mpc8309.h b/include/configs/km/km-mpc8309.h
deleted file mode 100644
index 0468ed5e83..0000000000
--- a/include/configs/km/km-mpc8309.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * High Level Configuration Options
- */
-
-#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
-
-/* QE microcode/firmware address */
-/* between the u-boot partition and env */
-
-/*
- * System IO Config
- */
-/* 0x14000180 SICR_1 */
-#ifndef CONFIG_SYS_SICRL
-#define CONFIG_SYS_SICRL (0			\
-		| SICR_1_UART1_UART1RTS		\
-		| SICR_1_I2C_CKSTOP		\
-		| SICR_1_IRQ_A_IRQ		\
-		| SICR_1_IRQ_B_IRQ		\
-		| SICR_1_GPIO_A_GPIO		\
-		| SICR_1_GPIO_B_GPIO		\
-		| SICR_1_GPIO_C_GPIO		\
-		| SICR_1_GPIO_D_GPIO		\
-		| SICR_1_GPIO_E_GPIO		\
-		| SICR_1_GPIO_F_GPIO		\
-		| SICR_1_USB_A_UART2S		\
-		| SICR_1_USB_B_UART2RTS		\
-		| SICR_1_FEC1_FEC1		\
-		| SICR_1_FEC2_FEC2		\
-		)
-#endif
-
-/* 0x00080400 SICR_2 */
-#define CONFIG_SYS_SICRH (0			\
-		| SICR_2_FEC3_FEC3		\
-		| SICR_2_HDLC1_A_HDLC1		\
-		| SICR_2_ELBC_A_LA		\
-		| SICR_2_ELBC_B_LCLK		\
-		| SICR_2_HDLC2_A_HDLC2		\
-		| SICR_2_USB_D_GPIO		\
-		| SICR_2_PCI_PCI		\
-		| SICR_2_HDLC1_B_HDLC1		\
-		| SICR_2_HDLC1_C_HDLC1		\
-		| SICR_2_HDLC2_B_GPIO		\
-		| SICR_2_HDLC2_C_HDLC2		\
-		| SICR_2_QUIESCE_B		\
-		)
-
-/* GPR_1 */
-#define CONFIG_SYS_GPR1  0x50008060
-
-#define CONFIG_SYS_DDRCDR (\
-	DDRCDR_EN | \
-	DDRCDR_PZ_MAXZ | \
-	DDRCDR_NZ_MAXZ | \
-	DDRCDR_M_ODR)
-
-#define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
-#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
-					 SDRAM_CFG_32_BE | \
-					 SDRAM_CFG_SREN | \
-					 SDRAM_CFG_HSE)
-
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
-#define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
-				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
-
-#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
-					 CSCONFIG_ODT_RD_NEVER | \
-					 CSCONFIG_ODT_WR_ONLY_CURRENT | \
-					 CSCONFIG_ROW_BIT_13 | \
-					 CSCONFIG_COL_BIT_10)
-
-#define CONFIG_SYS_DDR_MODE	0x47860242
-#define CONFIG_SYS_DDR_MODE2	0x8080c000
-
-#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
-				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
-				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
-				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
-				 (0 << TIMING_CFG0_WWT_SHIFT) | \
-				 (0 << TIMING_CFG0_RRT_SHIFT) | \
-				 (0 << TIMING_CFG0_WRT_SHIFT) | \
-				 (0 << TIMING_CFG0_RWT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
-				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
-				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
-				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
-				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
-				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
-				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
-				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
-				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
-				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
-				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
-				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
-				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
-				 (5 << TIMING_CFG2_CPO_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-
-#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
-#define CONFIG_SYS_KMBEC_FPGA_SIZE	128
-
-/* EEprom support */
-
-/* ethernet port connected to piggy (UEC2) */
-#define CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM		2       /* UCC3 */
-#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
-#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK12
-#define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR	0
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h
deleted file mode 100644
index bdd35cc7fb..0000000000
--- a/include/configs/kmtegr1.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- *                    Dave Liu <daveliu at freescale.com>
- *
- * Copyright (C) 2007 Logic Product Development, Inc.
- *                    Peter Barada <peterb at logicpd.com>
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- *                    Anton Vorontsov <avorontsov at ru.mvista.com>
- *
- * (C) Copyright 2010
- * Heiko Schocher, DENX Software Engineering, hs at denx.de.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-
-#define CONFIG_HOSTNAME   "kmtegr1"
-#define CONFIG_KM_UBI_PARTITION_NAME_BOOT	"ubi0"
-#define CONFIG_KM_UBI_PARTITION_NAME_APP	"ubi1"
-
-#define CONFIG_NAND_ECC_BCH
-#define CONFIG_NAND_KMETER1
-#define CONFIG_SYS_MAX_NAND_DEVICE		1
-#define NAND_MAX_CHIPS				1
-
-#define CONFIG_SYS_SICRL (0     \
-		| SICR_1_UART1_UART1RTS   \
-		| SICR_1_I2C_CKSTOP   \
-		| SICR_1_IRQ_A_IRQ    \
-		| SICR_1_IRQ_B_IRQ    \
-		| SICR_1_GPIO_A_GPIO    \
-		| SICR_1_GPIO_B_GPIO    \
-		| SICR_1_GPIO_C_GPIO    \
-		| SICR_1_GPIO_D_GPIO    \
-		| SICR_1_GPIO_E_LCS    \
-		| SICR_1_GPIO_F_GPIO    \
-		| SICR_1_USB_A_UART2S   \
-		| SICR_1_USB_B_UART2RTS   \
-		| SICR_1_FEC1_FEC1    \
-		| SICR_1_FEC2_FEC2    \
-	)
-
-/* include common defines/options for all Keymile boards */
-#include "km/keymile-common.h"
-#include "km/km-powerpc.h"
-#include "km/km-mpc83xx.h"
-#include "km/km-mpc8309.h"
-
-/* must be after the include because KMBEC_FPGA is otherwise undefined */
-#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
-
-#endif /* __CONFIG_H */
diff --git a/include/linux/immap_qe.h b/include/linux/immap_qe.h
index 022771fff5..45307f51c1 100644
--- a/include/linux/immap_qe.h
+++ b/include/linux/immap_qe.h
@@ -16,7 +16,7 @@
 #define QE_MURAM_SIZE		0xc000UL
 #define MAX_QE_RISC		2
 #define QE_NUM_OF_SNUM		28
-#elif defined(CONFIG_ARCH_MPC832X) || defined(CONFIG_ARCH_MPC8309)
+#elif defined(CONFIG_ARCH_MPC832X)
 #define QE_MURAM_SIZE		0x4000UL
 #define MAX_QE_RISC		1
 #define QE_NUM_OF_SNUM		28
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 2181a90b59..5926c8090a 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -340,85 +340,6 @@
 #define SICRH_TSOBI2_V3P3		(0 << 0)
 #define SICRH_TSOBI2_V2P5		(1 << 0)
 
-#elif defined(CONFIG_ARCH_MPC8309)
-/* SICR_1 */
-#define SICR_1_UART1_UART1S		(0 << (30-2))
-#define SICR_1_UART1_UART1RTS		(1 << (30-2))
-#define SICR_1_I2C_I2C			(0 << (30-4))
-#define SICR_1_I2C_CKSTOP		(1 << (30-4))
-#define SICR_1_IRQ_A_IRQ		(0 << (30-6))
-#define SICR_1_IRQ_A_MCP		(1 << (30-6))
-#define SICR_1_IRQ_B_IRQ		(0 << (30-8))
-#define SICR_1_IRQ_B_CKSTOP		(1 << (30-8))
-#define SICR_1_GPIO_A_GPIO		(0 << (30-10))
-#define SICR_1_GPIO_A_SD		(2 << (30-10))
-#define SICR_1_GPIO_A_DDR		(3 << (30-10))
-#define SICR_1_GPIO_B_GPIO		(0 << (30-12))
-#define SICR_1_GPIO_B_SD		(2 << (30-12))
-#define SICR_1_GPIO_B_QE		(3 << (30-12))
-#define SICR_1_GPIO_C_GPIO		(0 << (30-14))
-#define SICR_1_GPIO_C_CAN		(1 << (30-14))
-#define SICR_1_GPIO_C_DDR		(2 << (30-14))
-#define SICR_1_GPIO_C_LCS		(3 << (30-14))
-#define SICR_1_GPIO_D_GPIO		(0 << (30-16))
-#define SICR_1_GPIO_D_CAN		(1 << (30-16))
-#define SICR_1_GPIO_D_DDR		(2 << (30-16))
-#define SICR_1_GPIO_D_LCS		(3 << (30-16))
-#define SICR_1_GPIO_E_GPIO		(0 << (30-18))
-#define SICR_1_GPIO_E_CAN		(1 << (30-18))
-#define SICR_1_GPIO_E_DDR		(2 << (30-18))
-#define SICR_1_GPIO_E_LCS		(3 << (30-18))
-#define SICR_1_GPIO_F_GPIO		(0 << (30-20))
-#define SICR_1_GPIO_F_CAN		(1 << (30-20))
-#define SICR_1_GPIO_F_CK		(2 << (30-20))
-#define SICR_1_USB_A_USBDR		(0 << (30-22))
-#define SICR_1_USB_A_UART2S		(1 << (30-22))
-#define SICR_1_USB_B_USBDR		(0 << (30-24))
-#define SICR_1_USB_B_UART2S		(1 << (30-24))
-#define SICR_1_USB_B_UART2RTS		(2 << (30-24))
-#define SICR_1_USB_C_USBDR		(0 << (30-26))
-#define SICR_1_USB_C_QE_EXT		(3 << (30-26))
-#define SICR_1_FEC1_FEC1		(0 << (30-28))
-#define SICR_1_FEC1_GTM			(1 << (30-28))
-#define SICR_1_FEC1_GPIO		(2 << (30-28))
-#define SICR_1_FEC2_FEC2		(0 << (30-30))
-#define SICR_1_FEC2_GTM			(1 << (30-30))
-#define SICR_1_FEC2_GPIO		(2 << (30-30))
-/* SICR_2 */
-#define SICR_2_FEC3_FEC3		(0 << (30-0))
-#define SICR_2_FEC3_TMR			(1 << (30-0))
-#define SICR_2_FEC3_GPIO		(2 << (30-0))
-#define SICR_2_HDLC1_A_HDLC1		(0 << (30-2))
-#define SICR_2_HDLC1_A_GPIO		(1 << (30-2))
-#define SICR_2_HDLC1_A_TDM1		(2 << (30-2))
-#define SICR_2_ELBC_A_LA		(0 << (30-4))
-#define SICR_2_ELBC_B_LCLK		(0 << (30-6))
-#define SICR_2_HDLC2_A_HDLC2		(0 << (30-8))
-#define SICR_2_HDLC2_A_GPIO		(0 << (30-8))
-#define SICR_2_HDLC2_A_TDM2		(0 << (30-8))
-/* bits 10-11 unused */
-#define SICR_2_USB_D_USBDR		(0 << (30-12))
-#define SICR_2_USB_D_GPIO		(2 << (30-12))
-#define SICR_2_USB_D_QE_BRG		(3 << (30-12))
-#define SICR_2_PCI_PCI			(0 << (30-14))
-#define SICR_2_PCI_CPCI_HS		(2 << (30-14))
-#define SICR_2_HDLC1_B_HDLC1		(0 << (30-16))
-#define SICR_2_HDLC1_B_GPIO		(1 << (30-16))
-#define SICR_2_HDLC1_B_QE_BRG		(2 << (30-16))
-#define SICR_2_HDLC1_B_TDM1		(3 << (30-16))
-#define SICR_2_HDLC1_C_HDLC1		(0 << (30-18))
-#define SICR_2_HDLC1_C_GPIO		(1 << (30-18))
-#define SICR_2_HDLC1_C_TDM1		(2 << (30-18))
-#define SICR_2_HDLC2_B_HDLC2		(0 << (30-20))
-#define SICR_2_HDLC2_B_GPIO		(1 << (30-20))
-#define SICR_2_HDLC2_B_QE_BRG		(2 << (30-20))
-#define SICR_2_HDLC2_B_TDM2		(3 << (30-20))
-#define SICR_2_HDLC2_C_HDLC2		(0 << (30-22))
-#define SICR_2_HDLC2_C_GPIO		(1 << (30-22))
-#define SICR_2_HDLC2_C_TDM2		(2 << (30-22))
-#define SICR_2_HDLC2_C_QE_BRG		(3 << (30-22))
-#define SICR_2_QUIESCE_B		(0 << (30-24))
-
 #endif
 
 /*
@@ -610,63 +531,6 @@
 #define HRCWL_SVCOD_DIV_8		0x10000000
 #define HRCWL_SVCOD_DIV_2		0x20000000
 #define HRCWL_SVCOD_DIV_1		0x30000000
-#elif defined(CONFIG_ARCH_MPC8309)
-
-#define HRCWL_CEVCOD			0x000000C0
-#define HRCWL_CEVCOD_SHIFT		6
-/*
- * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012
- * these are different than with 8360, 832x
- */
-#define HRCWL_CE_PLL_VCO_DIV_2		0x00000000
-#define HRCWL_CE_PLL_VCO_DIV_4		0x00000040
-#define HRCWL_CE_PLL_VCO_DIV_8		0x00000080
-
-#define HRCWL_CEPDF			0x00000020
-#define HRCWL_CEPDF_SHIFT		5
-#define HRCWL_CE_PLL_DIV_1X1		0x00000000
-#define HRCWL_CE_PLL_DIV_2X1		0x00000020
-
-#define HRCWL_CEPMF			0x0000001F
-#define HRCWL_CEPMF_SHIFT		0
-#define HRCWL_CE_TO_PLL_1X16_		0x00000000
-#define HRCWL_CE_TO_PLL_1X2		0x00000002
-#define HRCWL_CE_TO_PLL_1X3		0x00000003
-#define HRCWL_CE_TO_PLL_1X4		0x00000004
-#define HRCWL_CE_TO_PLL_1X5		0x00000005
-#define HRCWL_CE_TO_PLL_1X6		0x00000006
-#define HRCWL_CE_TO_PLL_1X7		0x00000007
-#define HRCWL_CE_TO_PLL_1X8		0x00000008
-#define HRCWL_CE_TO_PLL_1X9		0x00000009
-#define HRCWL_CE_TO_PLL_1X10		0x0000000A
-#define HRCWL_CE_TO_PLL_1X11		0x0000000B
-#define HRCWL_CE_TO_PLL_1X12		0x0000000C
-#define HRCWL_CE_TO_PLL_1X13		0x0000000D
-#define HRCWL_CE_TO_PLL_1X14		0x0000000E
-#define HRCWL_CE_TO_PLL_1X15		0x0000000F
-#define HRCWL_CE_TO_PLL_1X16		0x00000010
-#define HRCWL_CE_TO_PLL_1X17		0x00000011
-#define HRCWL_CE_TO_PLL_1X18		0x00000012
-#define HRCWL_CE_TO_PLL_1X19		0x00000013
-#define HRCWL_CE_TO_PLL_1X20		0x00000014
-#define HRCWL_CE_TO_PLL_1X21		0x00000015
-#define HRCWL_CE_TO_PLL_1X22		0x00000016
-#define HRCWL_CE_TO_PLL_1X23		0x00000017
-#define HRCWL_CE_TO_PLL_1X24		0x00000018
-#define HRCWL_CE_TO_PLL_1X25		0x00000019
-#define HRCWL_CE_TO_PLL_1X26		0x0000001A
-#define HRCWL_CE_TO_PLL_1X27		0x0000001B
-#define HRCWL_CE_TO_PLL_1X28		0x0000001C
-#define HRCWL_CE_TO_PLL_1X29		0x0000001D
-#define HRCWL_CE_TO_PLL_1X30		0x0000001E
-#define HRCWL_CE_TO_PLL_1X31		0x0000001F
-
-#define HRCWL_SVCOD			0x30000000
-#define HRCWL_SVCOD_SHIFT		28
-#define HRCWL_SVCOD_DIV_2		0x00000000
-#define HRCWL_SVCOD_DIV_4		0x10000000
-#define HRCWL_SVCOD_DIV_8		0x20000000
-#define HRCWL_SVCOD_DIV_1		0x30000000
 #endif
 
 /*
@@ -1027,21 +891,6 @@
 #define SCCR_SATACM_1			0x00000055
 #define SCCR_SATACM_2			0x000000aa
 #define SCCR_SATACM_3			0x000000ff
-#elif defined(CONFIG_ARCH_MPC8309)
-/* SCCR bits - MPC8309 specific */
-#define SCCR_SDHCCM			0x0c000000
-#define SCCR_SDHCCM_SHIFT		26
-#define SCCR_SDHCCM_0			0x00000000
-#define SCCR_SDHCCM_1			0x04000000
-#define SCCR_SDHCCM_2			0x08000000
-#define SCCR_SDHCCM_3			0x0c000000
-
-#define SCCR_USBDRCM			0x00c00000
-#define SCCR_USBDRCM_SHIFT		22
-#define SCCR_USBDRCM_0			0x00000000
-#define SCCR_USBDRCM_1			0x00400000
-#define SCCR_USBDRCM_2			0x00800000
-#define SCCR_USBDRCM_3			0x00c00000
 #endif
 
 #define SCCR_PCIEXP1CM			0x00300000
-- 
2.37.0.rc2.2.g39c15e4



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