[PATCH v2] pci: Do not enable PCIe GEN3 link retrain workaround by default

[Simon Glass]

On Sat, 27 Aug 2022 at 06:30, Pali Rohár <pali at kernel.org> wrote:
>
> PCIe GEN3 link retrain workaround, specially designed for system with PCIe
> ASMedia ASM2824 Switch and other Endpoint devices, unconditionally increase
> size of all SPL binaries with PCIe support, even those which do not require it.
>
> Moreover this workaround is enabled for all existing hardware and also all
> future PCIe hardware, which opens a hole that other PCIe vendors may
> introduce same HW issue as on systems where this workaround is required and
> nobody would notice it because U-Boot automatically apply workaround for it.
>
> So do not unconditionally enable this workaround on all hardware. Instead
> introduce a new config option which is disabled by default. This decrease
> SPL size and also ensure that workaround is not blindly or inexactly
> enabled.
>
> To make workaround code local, move it into separate file, so pci_auto.c
> contains only generic auto configuration code.
>
> Signed-off-by: Pali Rohár <pali at kernel.org>
> ---
> Changes in v2:
> * Rename config option to CONFIG_PCIE_GEN3_RETRAIN_WORKAROUND as it is
>   generic workaround and does not have to be needed only for ASMedia switch
>   (moreover it looks like issue is triggered by combination of ASMedia
>    switch with other endpoint PCIe device)
> * Rephrase Kconfig help text as suggected by Stefan
> ---
>  drivers/pci/Kconfig                        |   9 +
>  drivers/pci/Makefile                       |   1 +
>  drivers/pci/pci_auto.c                     | 171 +------------------
>  drivers/pci/pcie_gen3_retrain_workaround.c | 183 +++++++++++++++++++++
>  4 files changed, 197 insertions(+), 167 deletions(-)
>  create mode 100644 drivers/pci/pcie_gen3_retrain_workaround.c

Reviewed-by: Simon Glass <sjg at chromium.org>