[PATCH] net: dw_eth_qos: Add 64-bit addressing
Ley Foon Tan
leyfoon.tan at starfivetech.com
Fri Dec 9 07:33:14 CET 2022
Set upper 32bit address for DMA descriptors and buffer address to support
64-bit addressing.
Signed-off-by: Ley Foon Tan <leyfoon.tan at starfivetech.com>
---
drivers/net/dwc_eth_qos.c | 36 ++++++++++++++++++++----------------
1 file changed, 20 insertions(+), 16 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index afc47b56ff..a21dbbda72 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -745,6 +745,7 @@ static int eqos_start(struct udevice *dev)
u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
ulong last_rx_desc;
ulong desc_pad;
+ ulong addr64;
debug("%s(dev=%p):\n", __func__, dev);
@@ -1008,25 +1009,25 @@ static int eqos_start(struct udevice *dev)
for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
struct eqos_desc *rx_desc = eqos_get_desc(eqos, i, true);
- rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
- (i * EQOS_MAX_PACKET_SIZE));
+
+ addr64 = (ulong)(eqos->rx_dma_buf + (i * EQOS_MAX_PACKET_SIZE));
+ rx_desc->des0 = lower_32_bits(addr64);
+ rx_desc->des1 = upper_32_bits(addr64);
rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
mb();
eqos->config->ops->eqos_flush_desc(rx_desc);
- eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf +
- (i * EQOS_MAX_PACKET_SIZE),
- EQOS_MAX_PACKET_SIZE);
+ eqos->config->ops->eqos_inval_buffer((void *)addr64, EQOS_MAX_PACKET_SIZE);
}
- writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
- writel((ulong)eqos_get_desc(eqos, 0, false),
- &eqos->dma_regs->ch0_txdesc_list_address);
+ addr64 = (ulong)eqos_get_desc(eqos, 0, false);
+ writel(upper_32_bits(addr64), &eqos->dma_regs->ch0_txdesc_list_haddress);
+ writel(lower_32_bits(addr64), &eqos->dma_regs->ch0_txdesc_list_address);
writel(EQOS_DESCRIPTORS_TX - 1,
&eqos->dma_regs->ch0_txdesc_ring_length);
- writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);
- writel((ulong)eqos_get_desc(eqos, 0, true),
- &eqos->dma_regs->ch0_rxdesc_list_address);
+ addr64 = (ulong)eqos_get_desc(eqos, 0, true);
+ writel(upper_32_bits(addr64), &eqos->dma_regs->ch0_rxdesc_list_haddress);
+ writel(lower_32_bits(addr64), &eqos->dma_regs->ch0_rxdesc_list_address);
writel(EQOS_DESCRIPTORS_RX - 1,
&eqos->dma_regs->ch0_rxdesc_ring_length);
@@ -1131,8 +1132,8 @@ static int eqos_send(struct udevice *dev, void *packet, int length)
eqos->tx_desc_idx++;
eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
- tx_desc->des0 = (ulong)eqos->tx_dma_buf;
- tx_desc->des1 = 0;
+ tx_desc->des0 = lower_32_bits((ulong)eqos->tx_dma_buf);
+ tx_desc->des1 = upper_32_bits((ulong)eqos->tx_dma_buf);
tx_desc->des2 = length;
/*
* Make sure that if HW sees the _OWN write below, it will see all the
@@ -1205,14 +1206,17 @@ static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
for (idx = eqos->rx_desc_idx - idx_mask;
idx <= eqos->rx_desc_idx;
idx++) {
+ ulong addr64;
+
rx_desc = eqos_get_desc(eqos, idx, true);
rx_desc->des0 = 0;
+ rx_desc->des1 = 0;
mb();
eqos->config->ops->eqos_flush_desc(rx_desc);
eqos->config->ops->eqos_inval_buffer(packet, length);
- rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
- (idx * EQOS_MAX_PACKET_SIZE));
- rx_desc->des1 = 0;
+ addr64 = (ulong)(eqos->rx_dma_buf + (idx * EQOS_MAX_PACKET_SIZE));
+ rx_desc->des0 = lower_32_bits(addr64);
+ rx_desc->des1 = upper_32_bits(addr64);
rx_desc->des2 = 0;
/*
* Make sure that if HW sees the _OWN write below,
--
2.25.1
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