[PATCH v1 01/17] riscv: cpu: jh7110: Add support for jh7110 SoC

[Yanhong Wang]

Add StarFive JH7110 SoC to support RISC-V arch.

Signed-off-by: Yanhong Wang <yanhong.wang at starfivetech.com>
---
 arch/riscv/cpu/jh7110/Makefile                | 10 ++++
 arch/riscv/cpu/jh7110/cpu.c                   | 23 ++++++++
 arch/riscv/cpu/jh7110/dram.c                  | 38 +++++++++++++
 arch/riscv/cpu/jh7110/spl.c                   | 56 +++++++++++++++++++
 .../include/asm/arch-jh7110/jh7110-regs.h     | 20 +++++++
 arch/riscv/include/asm/arch-jh7110/spl.h      | 13 +++++
 6 files changed, 160 insertions(+)
 create mode 100644 arch/riscv/cpu/jh7110/Makefile
 create mode 100644 arch/riscv/cpu/jh7110/cpu.c
 create mode 100644 arch/riscv/cpu/jh7110/dram.c
 create mode 100644 arch/riscv/cpu/jh7110/spl.c
 create mode 100644 arch/riscv/include/asm/arch-jh7110/jh7110-regs.h
 create mode 100644 arch/riscv/include/asm/arch-jh7110/spl.h

diff --git a/arch/riscv/cpu/jh7110/Makefile b/arch/riscv/cpu/jh7110/Makefile
new file mode 100644
index 0000000000..951c95631e
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 StarFive Technology Co., Ltd.
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y += spl.o
+else
+obj-y += cpu.o
+obj-y += dram.o
+endif
diff --git a/arch/riscv/cpu/jh7110/cpu.c b/arch/riscv/cpu/jh7110/cpu.c
new file mode 100644
index 0000000000..5da71908c0
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/cpu.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author:	Yanhong Wang <yanhong.wang at starfivetech.com>
+ */
+
+#include <asm/cache.h>
+#include <irq_func.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+	disable_interrupts();
+
+	cache_flush();
+
+	return 0;
+}
diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c
new file mode 100644
index 0000000000..4ce91aee9d
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/dram.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author:	Yanhong Wang <yanhong.wang at starfivetech.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+{
+	/*
+	 * Ensure that we run from first 4GB so that all
+	 * addresses used by U-Boot are 32bit addresses.
+	 *
+	 * This in-turn ensures that 32bit DMA capable
+	 * devices work fine because DMA mapping APIs will
+	 * provide 32bit DMA addresses only.
+	 */
+	if (IS_ENABLED(CONFIG_64BIT) && gd->ram_top > SZ_4G)
+		return SZ_4G;
+
+	return gd->ram_top;
+}
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
new file mode 100644
index 0000000000..a0aacacf7b
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author:	Yanhong Wang<yanhong.wang at starfivetech.com>
+ *
+ */
+
+#include <asm/csr.h>
+#include <dm.h>
+#include <log.h>
+
+#define CSR_U74_FEATURE_DISABLE	0x7c1
+
+int spl_soc_init(void)
+{
+	int ret;
+	struct udevice *dev;
+
+	/* DDR init */
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		return ret;
+	}
+
+	/* flash init */
+	ret = uclass_get_device(UCLASS_SPI_FLASH, 0, &dev);
+	if (ret) {
+		debug("SPI init failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+void harts_early_init(void)
+{
+	/*
+	 * Feature Disable CSR
+	 *
+	 * Clear feature disable CSR to '0' to turn on all features for
+	 * each core. This operation must be in M-mode.
+	 */
+	if (CONFIG_IS_ENABLED(RISCV_MMODE))
+		csr_write(CSR_U74_FEATURE_DISABLE, 0);
+
+	/* clear L2 LIM  memory
+	 * set __bss_end to 0x81FFFFF region to zero
+	 */
+	asm volatile("la t1, __bss_end\n\t"
+		"li t2, 0x81FFFFF\n\t"
+		"spl_clear_l2im:\n\t"
+		"sd zero, 0(t1)\n\t"
+		"addi t1, t1, 8\n\t"
+		"blt t1, t2, spl_clear_l2im\n\t");
+}
diff --git a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h
new file mode 100644
index 0000000000..a204fbcadf
--- /dev/null
+++ b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author:	Yanhong Wang <yanhong.wang at starfivetech.com>
+ *
+ */
+
+#ifndef __STARFIVE_JH7110_REGS_H
+#define __STARFIVE_JH7110_REGS_H
+
+#define JH7110_SYS_SYSCON		0x13030000
+#define JH7110_SYS_IOMUX		0x13040000
+#define JH7110_AON_SYSCON		0x17010000
+#define JH7110_SYS_CRG			0x13020000
+#define JH7110_AON_CRG			0x17000000
+
+#define JH7110_BOOT_MODE_SELECT_REG	0x1702002c
+#define JH7110_BOOT_MODE_SELECT_MASK	GENMASK(1, 0)
+
+#endif /* __STARFIVE_JH7110_REGS_H */
diff --git a/arch/riscv/include/asm/arch-jh7110/spl.h b/arch/riscv/include/asm/arch-jh7110/spl.h
new file mode 100644
index 0000000000..9e9e824365
--- /dev/null
+++ b/arch/riscv/include/asm/arch-jh7110/spl.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author:	Yanhong Wang <yanhong.wang at starfivetech.com>
+ *
+ */
+
+#ifndef _SPL_STARFIVE_H
+#define _SPL_STARFIVE_H
+
+int spl_soc_init(void);
+
+#endif /* _SPL_STARFIVE_H */
-- 
2.17.1