[PATCH] serial: ns16550: Enable clocks during probe

[Samuel Holland]

On 12/12/22 12:54, Tom Rini wrote:
> On Sun, Nov 27, 2022 at 11:48:34PM -0600, Samuel Holland wrote:
> 
>> If the UART bus or baud clock has a gate, it must be enabled before the
>> UART can be used.
>>
>> Signed-off-by: Samuel Holland <samuel at sholland.org>
>> Reviewed-by: Stefan Roese <sr at denx.de>
> 
> This breaks building on phycore-rk3288

I get:

binman: Error 1 running 'mkimage -d ./mkimage.simple-bin.mkimage -n
rk3288 -T rksd ./idbloader.img': Error: SPL image is too large (size
0x8800 than 0x8000)

Before applying this patch:

$ ls -l spl/u-boot-spl.bin
-rw-r--r-- 1 samuel samuel 32704 Dec 12 19:35 spl/u-boot-spl.bin

So the board was quite close to its SPL size limit already.

I was trying to be general with this patch, but I suppose for my
immediate purposes (Allwinner D1), I only care about the first clock. If
I use clk_get_by_index() instead of clk_get_bulk(), the phycore-rk3288
build passes with 4 bytes to spare:

$ ls -l spl/u-boot-spl.bin
-rw-r--r-- 1 samuel samuel 32760 Dec 12 19:36 spl/u-boot-spl.bin

I will send a v2, but I imagine some other unsuspecting patch will run
into this limit again before long.

Regards,
Samuel