[PATCH V3 2/2] spi: cadence_qspi: use STIG mode for small reads

[Pratyush Yadav]

On 25/11/22 11:29AM, Dhruva Gole wrote:
> Fix the issue where some flash chips like cypress S25HS256T return the
> value of the same register over and over in DAC mode.
> 
> For example in the TI K3-AM62x Processors refer [0] Technical Reference

I know where to find the useful information in this 12 thousand page 
long document since I used to work at TI. But other people might not 
find it so easy. It would be good to point to specific section numbers 
here to make this easier to understand and review. Also, this document 
does not contain the register map for the CQSPI controller. You should 
link that too.

> Manual there is a layer of digital logic in front of the QSPI/OSPI
> Drive when used in DAC mode. This is part of the Flash Subsystem (FSS)
> which provides access to external Flash devices. This operates by
> default in a 32 bit mode causing it to always align all data to 4 bytes

Is this new in AM62x? I do not remember seeing this on J7 class devices. 
I remember being able to read all registers from Cypress S28 flash 
without having to do anything special.

> from a 4byte aligned address. In some flash chips like cypress for
> example if we try to read some regs in DAC mode then it keeps sending the
> value of the first register that was requested and inorder to read the
> next reg, we have to stop and re-initiate a new transaction.
> 
> This causes wrong registers values to be read than what is desired when
> registers are read in DAC mode. Hence if the data.nbytes is very less
> then prefer STIG mode for such small reads.
> 
> [0] https://www.ti.com/lit/ug/spruiv7a/spruiv7a.pdf
> 
> Signed-off-by: Dhruva Gole <d-gole at ti.com>
> ---
>  drivers/spi/cadence_qspi.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
> index ab0a681c8376..5506f63ef078 100644
> --- a/drivers/spi/cadence_qspi.c
> +++ b/drivers/spi/cadence_qspi.c
> @@ -307,7 +307,13 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi,
>  				    priv->is_decoded_cs);
>  
>  	if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
> -		if (!op->addr.nbytes)
> +	/*
> +	 * Performing reads in DAC mode forces to read minimum 4 bytes
> +	 * which is unsupported on some flash devices during register
> +	 * reads, prefer STIG mode for such small reads.
> +	 */
> +		if (!op->addr.nbytes ||
> +		    op->data.nbytes < CQSPI_STIG_DATA_LEN_MAX)

                                    <= instead?

>  			mode = CQSPI_STIG_READ;
>  		else
>  			mode = CQSPI_READ;
> -- 
> 2.25.1
> 

-- 
Regards,
Pratyush Yadav