[PATCH v5 05/19] clk: at91: sam9x60: Add initial setup of UPLL and USBCK rates

Sergiu Moga sergiu.moga at microchip.com
Thu Dec 22 11:53:44 CET 2022


In order for some of the functionalities, such as the USB clocks,
to work properly we need some clocks to be properly initialised
at the very beginning of booting.

Signed-off-by: Sergiu Moga <sergiu.moga at microchip.com>
---


v1 -> v2:
- Adapted according to the additional 04/19 PATCH, now making use of
`at91_clk_setup`



v2 -> v5:
- No change



 drivers/clk/at91/sam9x60.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
index 14c2ffcac1..e2f72446d5 100644
--- a/drivers/clk/at91/sam9x60.c
+++ b/drivers/clk/at91/sam9x60.c
@@ -378,6 +378,31 @@ static const struct {
 	{ .n = "dbgu_gclk",   .id = 47, },
 };
 
+/**
+ * Clock setup description
+ * @cid:	clock id corresponding to clock subsystem
+ * @pid:	parent clock id corresponding to clock subsystem
+ * @rate:	clock rate
+ * @prate:	parent rate
+ */
+static const struct pmc_clk_setup sam9x60_clk_setup[] = {
+	{
+		.cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_FRAC),
+		.rate = 960000000,
+	},
+
+	{
+		.cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV),
+		.rate = 480000000,
+	},
+
+	{
+		.cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_USBCK),
+		.pid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV),
+		.rate = 48000000,
+	},
+};
+
 #define prepare_mux_table(_allocs, _index, _dst, _src, _num, _label)	\
 	do {								\
 		int _i;							\
@@ -668,6 +693,11 @@ static int sam9x60_clk_probe(struct udevice *dev)
 		clk_dm(AT91_TO_CLK_ID(PMC_TYPE_GCK, sam9x60_gck[i].id), c);
 	}
 
+	/* Setup clocks. */
+	ret = at91_clk_setup(sam9x60_clk_setup, ARRAY_SIZE(sam9x60_clk_setup));
+	if (ret)
+		goto fail;
+
 	return 0;
 
 fail:
-- 
2.34.1



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