[PATCH 09/18] Convert CONFIG_USB_EHCI_TXFIFO_THRESH to Kconfig

[Tom Rini]

This converts the following to Kconfig:
   CONFIG_USB_EHCI_TXFIFO_THRESH

Signed-off-by: Tom Rini <trini at konsulko.com>
---
 README                            |  3 ---
 drivers/usb/host/Kconfig          | 11 +++++++++++
 include/configs/tegra114-common.h |  3 ---
 include/configs/tegra124-common.h |  3 ---
 include/configs/tegra20-common.h  |  8 --------
 include/configs/tegra210-common.h |  3 ---
 include/configs/tegra30-common.h  |  3 ---
 7 files changed, 11 insertions(+), 23 deletions(-)

diff --git a/README b/README
index 9800359e5dfe..3603a9a46a37 100644
--- a/README
+++ b/README
@@ -793,9 +793,6 @@ The following options need to be configured:
 		Supported are USB Keyboards and USB Floppy drives
 		(TEAC FD-05PUB).
 
-		CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
-		txfilltuning field in the EHCI controller on reset.
-
 		CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2
 		HW module registers.
 
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 413bec0f4a1a..9c9d4dc947e4 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -284,6 +284,17 @@ config USB_EHCI_FSL
 	select EHCI_HCD_INIT_AFTER_RESET
 	---help---
 	  Enables support for the on-chip EHCI controller on FSL chips.
+
+config USB_EHCI_TXFIFO_THRESH
+	hex
+	depends on USB_EHCI_TEGRA
+	default 0x10
+	help
+	  This parameter affects a TXFILLTUNING field that controls how much
+	  data is sent to the latency fifo before it is sent to the wire.
+	  Without this parameter, the default (2) causes occasional Data Buffer
+	  Errors in OUT packets depending on the buffer address and size.
+
 endif # USB_EHCI_HCD
 
 config USB_OHCI_HCD
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
index 742083158948..87ec1f5a99d6 100644
--- a/include/configs/tegra114-common.h
+++ b/include/configs/tegra114-common.h
@@ -55,7 +55,4 @@
 
 /* Defines for SPL */
 
-/* For USB EHCI controller */
-#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
-
 #endif /* _TEGRA114_COMMON_H_ */
diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h
index 314486a1bcbd..f509784a8681 100644
--- a/include/configs/tegra124-common.h
+++ b/include/configs/tegra124-common.h
@@ -57,9 +57,6 @@
 
 /* Defines for SPL */
 
-/* For USB EHCI controller */
-#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
-
 /* GPU needs setup */
 #define CONFIG_TEGRA_GPU
 
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index a2b14d8ead86..71867bb6baac 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -69,12 +69,4 @@
 #define TEGRA_LP0_VEC
 #endif
 
-/*
- * This parameter affects a TXFILLTUNING field that controls how much data is
- * sent to the latency fifo before it is sent to the wire. Without this
- * parameter, the default (2) causes occasional Data Buffer Errors in OUT
- * packets depending on the buffer address and size.
- */
-#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
-
 #endif /* _TEGRA20_COMMON_H_ */
diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h
index 3ba12bec0eed..e510820786e4 100644
--- a/include/configs/tegra210-common.h
+++ b/include/configs/tegra210-common.h
@@ -46,9 +46,6 @@
 	"fdt_addr_r=0x83000000\0" \
 	"ramdisk_addr_r=0x83420000\0"
 
-/* For USB EHCI controller */
-#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
-
 /* GPU needs setup */
 #define CONFIG_TEGRA_GPU
 
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index a68da5ddfc89..04fcf11ed82d 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -52,7 +52,4 @@
 
 /* Defines for SPL */
 
-/* For USB EHCI controller */
-#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
-
 #endif /* _TEGRA30_COMMON_H_ */
-- 
2.25.1