[PATCH 4/4] spi: synquacer: simplify tx completion checking

[Tom Rini]

On Tue, May 17, 2022 at 05:41:39PM +0900, Masahisa Kojima wrote:

> There is a TX-FIFO and Shift Register empty(TFES) status
> bit in spi controller. This commit checks the TFES bit
> to wait the TX transfer completes.
> 
> Signed-off-by: Masahisa Kojima <masahisa.kojima at linaro.org>
> Signed-off-by: Satoru Okamoto <okamoto.satoru at socionext.com>
> Acked-by: Jassi Brar <jaswinder.singh at linaro.org>

Applied to u-boot/next, thanks!

-- 
Tom
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