[PATCH V2 02/17] imx: imx8m[m/n]_beacon: Enable SPL_DM_SERIAL

Adam Ford aford173 at gmail.com
Mon Jun 13 16:36:13 CEST 2022


On Sat, Jun 11, 2022 at 6:38 AM Peng Fan (OSS) <peng.fan at oss.nxp.com> wrote:
>
> From: Peng Fan <peng.fan at nxp.com>
>
> Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already
> marked with u-boot,dm-spl.
> Move preloader_console_init after spl_init to make sure driver
> model work.

For what it's worth, the series doesn't appear to apply cleanly on the
current master, but I tested a Nano in addition to the Mini that I
tested before.

>
> Signed-off-by: Peng Fan <peng.fan at nxp.com>
> Tested-by: Adam Ford <aford173 at gmail.com> #imx8mm_beacon

Tested-by: Adam Ford <aford173 at gmail.com> #imx8mn_beacon

> Reviewed-by: Fabio Estevam <festevam at denx.de>
> ---
>  board/beacon/imx8mm/spl.c          | 12 ++----------
>  board/beacon/imx8mn/spl.c          | 11 ++---------
>  configs/imx8mm_beacon_defconfig    |  1 -
>  configs/imx8mn_beacon_2g_defconfig |  1 -
>  configs/imx8mn_beacon_defconfig    |  1 -
>  include/configs/imx8mm_beacon.h    |  2 --
>  include/configs/imx8mn_beacon.h    |  2 --
>  7 files changed, 4 insertions(+), 26 deletions(-)
>
> diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c
> index 12266b22a42..f92b4c3ed0a 100644
> --- a/board/beacon/imx8mm/spl.c
> +++ b/board/beacon/imx8mm/spl.c
> @@ -59,14 +59,8 @@ int board_fit_config_name_match(const char *name)
>  }
>  #endif
>
> -#define UART_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
>  #define WDOG_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
>
> -static iomux_v3_cfg_t const uart_pads[] = {
> -       IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> -       IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> -};
> -
>  static iomux_v3_cfg_t const wdog_pads[] = {
>         IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
>  };
> @@ -79,8 +73,6 @@ int board_early_init_f(void)
>
>         set_wdog_reset(wdog);
>
> -       imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
> -
>         return 0;
>  }
>
> @@ -128,8 +120,6 @@ void board_init_f(ulong dummy)
>
>         timer_init();
>
> -       preloader_console_init();
> -
>         /* Clear the BSS. */
>         memset(__bss_start, 0, __bss_end - __bss_start);
>
> @@ -139,6 +129,8 @@ void board_init_f(ulong dummy)
>                 hang();
>         }
>
> +       preloader_console_init();
> +
>         ret = uclass_get_device_by_name(UCLASS_CLK,
>                                         "clock-controller at 30380000",
>                                         &dev);
> diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c
> index bb51be01c52..4563446db19 100644
> --- a/board/beacon/imx8mn/spl.c
> +++ b/board/beacon/imx8mn/spl.c
> @@ -68,7 +68,6 @@ int board_fit_config_name_match(const char *name)
>  }
>  #endif
>
> -#define UART_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
>  #define WDOG_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
>  #define PWM1_PAD_CTRL (PAD_CTL_FSEL2 | PAD_CTL_DSE6)
>
> @@ -76,11 +75,6 @@ static iomux_v3_cfg_t const pwm_pads[] = {
>         IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL),
>  };
>
> -static iomux_v3_cfg_t const uart_pads[] = {
> -       IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> -       IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> -};
> -
>  static iomux_v3_cfg_t const wdog_pads[] = {
>         IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
>  };
> @@ -95,7 +89,6 @@ int board_early_init_f(void)
>         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
>         set_wdog_reset(wdog);
>
> -       imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
>         init_uart_clk(1);
>
>         return 0;
> @@ -114,14 +107,14 @@ void board_init_f(ulong dummy)
>
>         timer_init();
>
> -       preloader_console_init();
> -
>         ret = spl_init();
>         if (ret) {
>                 debug("spl_init() failed: %d\n", ret);
>                 hang();
>         }
>
> +       preloader_console_init();
> +
>         enable_tzc380();
>
>         /* DDR initialization */
> diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
> index 417ece1ef8c..e1acf7e8810 100644
> --- a/configs/imx8mm_beacon_defconfig
> +++ b/configs/imx8mm_beacon_defconfig
> @@ -125,7 +125,6 @@ CONFIG_SPL_DM_REGULATOR_FIXED=y
>  CONFIG_DM_REGULATOR_GPIO=y
>  CONFIG_CONS_INDEX=2
>  CONFIG_DM_SERIAL=y
> -# CONFIG_SPL_DM_SERIAL is not set
>  CONFIG_MXC_UART=y
>  CONFIG_SPI=y
>  CONFIG_DM_SPI=y
> diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig
> index 5b9b3715b34..cadef45028d 100644
> --- a/configs/imx8mn_beacon_2g_defconfig
> +++ b/configs/imx8mn_beacon_2g_defconfig
> @@ -127,7 +127,6 @@ CONFIG_DM_REGULATOR_FIXED=y
>  CONFIG_DM_REGULATOR_GPIO=y
>  CONFIG_DM_RESET=y
>  CONFIG_DM_SERIAL=y
> -# CONFIG_SPL_DM_SERIAL is not set
>  CONFIG_MXC_UART=y
>  CONFIG_SPI=y
>  CONFIG_DM_SPI=y
> diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig
> index b296898d6db..357109e32e5 100644
> --- a/configs/imx8mn_beacon_defconfig
> +++ b/configs/imx8mn_beacon_defconfig
> @@ -131,7 +131,6 @@ CONFIG_DM_REGULATOR_FIXED=y
>  CONFIG_DM_REGULATOR_GPIO=y
>  CONFIG_DM_RESET=y
>  CONFIG_DM_SERIAL=y
> -# CONFIG_SPL_DM_SERIAL is not set
>  CONFIG_MXC_UART=y
>  CONFIG_SPI=y
>  CONFIG_DM_SPI=y
> diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h
> index 897eac66b14..899d2ec34f9 100644
> --- a/include/configs/imx8mm_beacon.h
> +++ b/include/configs/imx8mm_beacon.h
> @@ -80,6 +80,4 @@
>  #define PHYS_SDRAM                     0x40000000
>  #define PHYS_SDRAM_SIZE                0x80000000 /* 2GB DDR */
>
> -#define CONFIG_MXC_UART_BASE           UART_BASE_ADDR(2)
> -
>  #endif
> diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h
> index 99cbc1d07c8..cadad050d07 100644
> --- a/include/configs/imx8mn_beacon.h
> +++ b/include/configs/imx8mn_beacon.h
> @@ -96,6 +96,4 @@
>  #define PHYS_SDRAM_SIZE                0x40000000 /* 1GB DDR */
>  #endif
>
> -#define CONFIG_MXC_UART_BASE           UART_BASE_ADDR(2)
> -
>  #endif
> --
> 2.36.0
>


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