[PATCH v3 06/23] microblaze: Fix stack protection behavior

[Michal Simek]

When U-Boot starts stack protection can be already enabled that's why setup
the lowest possible SLR value which is address 0. And the highest possible
stack in front of U-Boot. That's why you should never load U-Boot to the
beginning of DDR. There must be some space reserved. Code is using this
location for early malloc space, early global data and stack.

Signed-off-by: Michal Simek <michal.simek at amd.com>
---

(no changes since v1)

 arch/microblaze/cpu/start.S | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 9e00eef1f4b6..715ef37b39d9 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -15,8 +15,9 @@
 _start:
 	mts	rmsr, r0	/* disable cache */
 
-	addi	r8, r0, _end
-	mts	rslr, r8
+	mts	rslr, r0
+	addi	r8, r0, _start
+	mts	rshr, r8
 
 #if defined(CONFIG_SPL_BUILD)
 	addi	r1, r0, CONFIG_SPL_STACK_ADDR
-- 
2.36.1