[PATCH v2 00/11] Add Chameleon v3 support
Chee, Tien Fong
tien.fong.chee at intel.com
Wed Jun 15 13:27:45 CEST 2022
Hi,
> -----Original Message-----
> From: Paweł Anikiel <pan at semihalf.com>
> Sent: Wednesday, 15 June, 2022 7:08 PM
> To: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
> Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Simon Glass
> <sjg at chromium.org>; Fabio Estevam <festevam at denx.de>; Jagan Teki
> <jagan at amarulasolutions.com>; Andre Przywara <andre.przywara at arm.com>;
> Armstrong, Neil <narmstrong at baylibre.com>; Peter Robinson
> <pbrobinson at gmail.com>; Tim Harvey <tharvey at gateworks.com>; Ying-Chun
> Liu <paul.liu at linaro.org>; Christian Hewitt <christianshewitt at gmail.com>;
> adrian.fiergolski at fastree3d.com; Marek Behún <marek.behun at nic.cz>; Denk,
> Wolfgang <wd at denx.de>; Lim, Elly Siew Chin <elly.siew.chin.lim at intel.com>;
> Chee, Tien Fong <tien.fong.chee at intel.com>; Michal Simek
> <michal.simek at xilinx.com>; Vasut, Marek <marex at denx.de>; Marcin Wojtas
> <mw at semihalf.com>
> Subject: Re: [PATCH v2 00/11] Add Chameleon v3 support
>
> On Thu, May 26, 2022 at 4:37 PM Paweł Anikiel <pan at semihalf.com> wrote:
> >
> > The Google Chameleon v3 is a board made for testing both video and
> > audio interfaces of external devices. It has a connector compatible
> > with the
> > Mercury+ AA1 module, which itself contains an Arria 10 SoCFPGA. The
> > Mercury+ AA1
> > module comes in a few different configurations, the Chameleon V3
> > supports
> > ME-AA1-270-3E4-D11 and ME-AA1-480-2I3-D12E.
> >
> > This patchset adds support for the Chameleon v3 (both versions), as
> > well as some bugfixes and optimizations, mostly in Arria 10 code.
> >
> > V2:
> > Adjust devicetrees so that they work both in u-boot and linux
> > Put u-boot-specific parts of devicetrees into *-u-boot.dtsi files
> > Minor changes in Kconfig, defconfig, and config.h
> >
> > Paweł Anikiel (11):
> > arm: dts: Add Mercury+ AA1 devicetrees
> > arm: dts: Add Chameleonv3 handoff headers
> > arm: dts: Add Chameleonv3 devicetrees
> > board: Add Chameleonv3 board dir
> > config: Add Chameleonv3 config
> > misc: atsha204a: Increase wake delay by tWHI
> > sysreset: socfpga: Use parent device for reading base address
> > socfpga: arria10: Replace delays with busy waiting in cm_full_cfg
> > socfpga: arria10: Improve bitstream loading speed
> > socfpga: arria10: Wait for fifo empty after writing bitstream
> > socfpga: arria10: Allow dcache_enable before relocation
> >
> > arch/arm/dts/Makefile | 2 +
> > arch/arm/dts/socfpga_arria10_chameleonv3.dts | 90 ++++++
> > ...fpga_arria10_chameleonv3_270_3-u-boot.dtsi | 8 +
> > .../dts/socfpga_arria10_chameleonv3_270_3.dts | 5 +
> > ...ocfpga_arria10_chameleonv3_270_3_handoff.h | 305
> ++++++++++++++++++
> > ...fpga_arria10_chameleonv3_480_2-u-boot.dtsi | 8 +
> > .../dts/socfpga_arria10_chameleonv3_480_2.dts | 5 +
> > ...ocfpga_arria10_chameleonv3_480_2_handoff.h | 305
> ++++++++++++++++++
> > .../socfpga_arria10_mercury_aa1-u-boot.dtsi | 54 ++++
> > arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi | 72 +++++
> > arch/arm/mach-socfpga/Kconfig | 7 +
> > arch/arm/mach-socfpga/clock_manager.c | 7 +-
> > arch/arm/mach-socfpga/clock_manager_arria10.c | 12 +-
> > .../mach-socfpga/include/mach/clock_manager.h | 4 +
> > arch/arm/mach-socfpga/misc_arria10.c | 26 ++
> > board/google/chameleonv3/Makefile | 5 +
> > board/google/chameleonv3/board.c | 27 ++
> > board/google/chameleonv3/fpga.its | 28 ++
> > board/google/chameleonv3/fpga_early_io.its | 35 ++
> > board/google/chameleonv3/mercury_aa1.c | 43 +++
> > board/google/chameleonv3/mercury_aa1.h | 12 +
> > configs/socfpga_chameleonv3_defconfig | 29 ++
> > drivers/fpga/socfpga_arria10.c | 28 +-
> > drivers/misc/atsha204a-i2c.c | 5 +-
> > drivers/sysreset/sysreset_socfpga.c | 2 +-
> > include/configs/socfpga_chameleonv3.h | 44 +++
> > 26 files changed, 1154 insertions(+), 14 deletions(-) create mode
> > 100644 arch/arm/dts/socfpga_arria10_chameleonv3.dts
> > create mode 100644
> > arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
> > create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
> > create mode 100644
> > arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h
> > create mode 100644
> > arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
> > create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts
> > create mode 100644
> > arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h
> > create mode 100644
> > arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
> > create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
> > create mode 100644 board/google/chameleonv3/Makefile create mode
> > 100644 board/google/chameleonv3/board.c create mode 100644
> > board/google/chameleonv3/fpga.its create mode 100644
> > board/google/chameleonv3/fpga_early_io.its
> > create mode 100644 board/google/chameleonv3/mercury_aa1.c
> > create mode 100644 board/google/chameleonv3/mercury_aa1.h
> > create mode 100644 configs/socfpga_chameleonv3_defconfig
> > create mode 100644 include/configs/socfpga_chameleonv3.h
> >
> > --
> > 2.36.1.124.g0e6072fb45-goog
> >
>
> Hi,
>
> Could you please take a look? Do you have any comments or remarks to the
> patchset?
All looks fine to me, I'm in the progress to consolidate all socfpga patches for PR this Friday.
Thanks.
>
> Regards,
> Paweł
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