[Rock Pi 4+] Mainline LPDDR4 RAM initialisation is not sufficient to boot successfully
cym at rock-chips.com
cym at rock-chips.com
Fri Jun 17 14:06:06 CEST 2022
Could you help us to get the DRAM part number which initialization failures on the Rock Pi 4+.
We have found that some LPDDR4 abnormal operation at 50MHz.
I think you can try that use 400MHz to detect capacity.
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index c0a06dcaed..810f9a98c9 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -2538,24 +2538,42 @@ static int lpddr4_set_ctl(struct dram_info *dram,
return 0;
}
-static int lpddr4_set_rate(struct dram_info *dram,
+static int lpddr4_set_rate_0(struct dram_info *dram,
struct rk3399_sdram_params *params)
{
- u32 ctl_fn;
+ u32 ctl_fn = 0;
u32 phy_fn;
- for (ctl_fn = 0; ctl_fn < 2; ctl_fn++) {
- phy_fn = lpddr4_get_phy_fn(params, ctl_fn);
+ phy_fn = lpddr4_get_phy_fn(params, ctl_fn);
- lpddr4_set_phy(dram, params, phy_fn, &dfs_cfgs_lpddr4[ctl_fn]);
- lpddr4_set_ctl(dram, params, ctl_fn,
- dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq);
+ lpddr4_set_phy(dram, params, phy_fn, &dfs_cfgs_lpddr4[ctl_fn]);
+ lpddr4_set_ctl(dram, params, ctl_fn,
+ dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq);
- if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG))
- printf("%s: change freq to %d mhz %d, %d\n", __func__,
- dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq,
- ctl_fn, phy_fn);
- }
+ if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG))
+ printf("%s: change freq to %d mhz %d, %d\n", __func__,
+ dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq,
+ ctl_fn, phy_fn);
+
+ return 0;
+}
+
+static int lpddr4_set_rate_1(struct dram_info *dram,
+ struct rk3399_sdram_params *params)
+{
+ u32 ctl_fn = 1;
+ u32 phy_fn;
+
+ phy_fn = lpddr4_get_phy_fn(params, ctl_fn);
+
+ lpddr4_set_phy(dram, params, phy_fn, &dfs_cfgs_lpddr4[ctl_fn]);
+ lpddr4_set_ctl(dram, params, ctl_fn,
+ dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq);
+
+ if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG))
+ printf("%s: change freq to %d mhz %d, %d\n", __func__,
+ dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq,
+ ctl_fn, phy_fn);
return 0;
}
@@ -2955,6 +2973,11 @@ static int sdram_init(struct dram_info *dram,
params->ch[ch].cap_info.rank = rank;
}
+ #if defined(CONFIG_RAM_RK3399_LPDDR4)
+ lpddr4_set_rate_0(dram, params);
+ params->base.ddr_freq = dfs_cfgs_lpddr4[0].base.ddr_freq / MHz;
+ #endif
+
params->base.num_channels = 0;
for (channel = 0; channel < 2; channel++) {
const struct chan_info *chan = &dram->chan[channel];
@@ -3058,7 +3081,7 @@ static const struct sdram_rk3399_ops rk3399_ops = {
.get_phy_index_params = get_phy_index_params,
#else
.data_training_first = lpddr4_mr_detect,
- .set_rate_index = lpddr4_set_rate,
+ .set_rate_index = lpddr4_set_rate_1,
.modify_param = lpddr4_modify_param,
.get_phy_index_params = lpddr4_get_phy_index_params,
#endif
From: Lee Jones
Date: 2022-06-17 03:15
To: u-boot; linux-rockchip
CC: wxt; kever.yang; zhangqing; derrick.huang; chenjh; hisping.lin; typ; cwz; chenfen; jagan; sjg; cym; pgwipeout; adelva; rammuthiah
Subject: Re: [Rock Pi 4+] Mainline LPDDR4 RAM initialisation is not sufficient to boot successfully
On Wed, 25 May 2022, Lee Jones wrote:
> Good afternoon,
>
> There appear to be a number of issues with the Rockchip rk3399 DDR RAM
> initialisation sequence in Mainline. Specifically, I'm seeing
> consistent failures on the Rock Pi 4+ during early boot.
Can anyone from Rockchip help with this please?
What does the binary blob [0] do differently to the U-boot
implementation.
Are you able to publish the source for the DDR binary blob?
Please help me fix U-boot.
[0] https://github.com/rockchip-linux/rkbin/blob/master/bin/rk33/rk3399_ddr_933MHz_v1.25.bin
> A typical failure looks something like this:
>
> U-Boot TPL 2022.07-rc3-00005-g1b04a961c6 (May 25 2022 - 11:09:19)
> Channel 0: LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB
> Channel 1: col error
> Cap error!
> 256B stride
> lpddr4_set_rate: change freq to 400000000 mhz 0, 1
> lpddr4_set_rate: change freq to 800000000 mhz 1, 0
> Trying to boot from BOOTROM
> Returning to boot ROM...
>
> Even when the system boots to a terminal, which happens very
> infrequently, the LPDDR4 RAM chip at Channel 1 can have conflicting
> discovery information printed during TPL. The following 3 lines were
> printed during successive reboots using the same SD card with no
> changes:
>
> # Boot 1:
> BW=32 Col=9 Bk=4 CS0 Row=16/15 CS=1 Die BW=16 Size=384MB
>
> # Boot 2:
> BW=32 Col=10 Bk=4 CS0 Row=16/15 CS=1 Die BW=16 Size=768MB
>
> # Boot 3:
> BW=32 Col=10 Bk=4 CS0 Row=15 CS=1 Die BW=16 Size=512MB
>
> The story changes when I build the idbloader.img image with Rockchip's
> TBL (?) binary blob [0]. With that built in, presumably in place of
> the upstream TBL, both RAM chips are successfully enumerated and boot
> succeeds with 100% success rate:
>
> tools/mkimage -n rk3399 -T rksd -d \
> rk3399_ddr_933MHz_v1.25.bin:spl/u-boot-spl.bin idbloader.img
>
> Another thing that is very different between the 2 is the initial
> frequency the LPDDR4 chips are clocked at. Using the upstream TBL
> version, the default is 50Mhz, which seems very low. If using the
> Rockchip supplied binary blob file, this is increased to a respectable
> 416MHz:
>
> # Mainline
> Channel 0: LPDDR4, 50MHz
>
> # Rockchip TBL blob
> Channel 0: LPDDR4,416MHz
>
> One thing I did try was to load in the 400Mhz configuration settings
> from drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc as the default
> initial values, instead of the 50MHz default taken from
> arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi, but this failed in a number
> of ways:
>
> Setting clock: Freq: 400MHz (400000000)
> Calling SDRAM init: 2 Channels
> Starting SDRAM initialization...
> mr5:0 mr12:0 mr14:0
> Training failed for rank 2, ch 0 (ret: -22)
> mr5:0 mr12:0 mr14:0
> Training failed for rank 1, ch 0 (ret: -22)
> mr5:0 mr12:0 mr14:0
> Training failed for rank 2, ch 1 (ret: -22)
> mr5:0 mr12:0 mr14:0
> Training failed for rank 1, ch 1 (ret: -22)
> Rank for Channel 1 is 0x0
> Rank for Channel 0 is 0x0
> Rank for Channel 1 is 0x0
> sdram_init: LPDDR4 - 400MHz failed!
> rk3399_dmc_init DRAM init failed -22
>
> So my question is; does Rockchip, or anyone else for that matter, have
> any plans on updating Mainline U-Boot with the upgraded/working LPDDR4
> initialisation sequence?
>
> As ever, any information / help would be gratefully received.
>
> NB: If I have missed any critical people out from this discussion,
> please feel free to loop as many of them in as you see fit.
>
> Kind regards,
> Lee
>
> [0] https://github.com/rockchip-linux/rkbin/blob/master/bin/rk33/rk3399_ddr_933MHz_v1.25.bin
>
--
Lee Jones [李琼斯]
Principal Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
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