[PATCH 2/3] Set/clear reset_req bit before/after PR
Jit Loon Lim
jit.loon.lim at intel.com
Mon Nov 7 14:33:50 CET 2022
From: "Chew, Chiau Ee" <chiau.ee.chew at intel.com>
HSD #1508949110: For Agilex and Stratix10, before FPGA Partial Reconfiguration (PR)
operation, SW need to set reset_req bit in freeze_csr_ctrl register
to reset PR region. The same bit need to be cleared after FPGA PR
operation is done.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew at intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim at intel.com>
---
drivers/fpga/intel_pr.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/fpga/intel_pr.c b/drivers/fpga/intel_pr.c
index 6637425452..a0a758488b 100644
--- a/drivers/fpga/intel_pr.c
+++ b/drivers/fpga/intel_pr.c
@@ -81,10 +81,17 @@ static int intel_freeze_br_do_freeze(unsigned int region)
writel(FREEZE_CSR_CTRL_FREEZE_REQ, addr + FREEZE_CSR_CTRL_OFFSET);
- return wait_for_bit_le32((const u32 *)(addr +
+ ret = wait_for_bit_le32((const u32 *)(addr +
FREEZE_CSR_STATUS_OFFSET),
FREEZE_CSR_STATUS_FREEZE_REQ_DONE, true,
FREEZE_TIMEOUT, false);
+
+ if (ret)
+ writel(0, addr + FREEZE_CSR_CTRL_OFFSET);
+ else
+ writel(FREEZE_CSR_CTRL_RESET_REQ, addr + FREEZE_CSR_CTRL_OFFSET);
+
+ return ret;
}
static int intel_freeze_br_do_unfreeze(unsigned int region)
@@ -97,6 +104,8 @@ static int intel_freeze_br_do_unfreeze(unsigned int region)
if (ret)
return ret;
+ writel(0, addr + FREEZE_CSR_CTRL_OFFSET);
+
status = readl(addr + FREEZE_CSR_STATUS_OFFSET);
if (status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE)
@@ -106,10 +115,14 @@ static int intel_freeze_br_do_unfreeze(unsigned int region)
writel(FREEZE_CSR_CTRL_UNFREEZE_REQ, addr + FREEZE_CSR_CTRL_OFFSET);
- return wait_for_bit_le32((const u32 *)(addr +
+ ret = wait_for_bit_le32((const u32 *)(addr +
FREEZE_CSR_STATUS_OFFSET),
FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE, true,
FREEZE_TIMEOUT, false);
+
+ writel(0, addr + FREEZE_CSR_CTRL_OFFSET);
+
+ return ret;
}
static int do_pr(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
--
2.26.2
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