[PATCH] arm64: dts: imx8m{m, n}-venice-gw7902: add gpio pins for new board revision
Tim Harvey
tharvey at gateworks.com
Fri Nov 11 16:55:46 CET 2022
Add gpio pins present on new board revision:
* LTE modem support (imx8mm-gw7902 only)
- lte_pwr#
- lte_rst
- lte_int
* M2 power enable
- m2_pwr_en
* off-board 4.0V supply
- vdd_4p0_en
Signed-off-by: Tim Harvey <tharvey at gateworks.com>
---
arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi | 14 ++++++++++++++
arch/arm/dts/imx8mm-venice-gw7902.dts | 12 ++++++++----
arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi | 14 ++++++++++++++
arch/arm/dts/imx8mn-venice-gw7902.dts | 8 ++++----
4 files changed, 40 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi
index f21e46b12dd7..d58a7d14b631 100644
--- a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi
@@ -6,6 +6,13 @@
#include "imx8mm-venice-u-boot.dtsi"
&gpio1 {
+ m2pwren {
+ gpio-hog;
+ output-low;
+ gpios = <8 GPIO_ACTIVE_HIGH>;
+ line-name = "m2_pwren";
+ };
+
m2rst {
gpio-hog;
output-low;
@@ -96,6 +103,13 @@
line-name = "app_gpio1";
};
+ vdd4p0en {
+ gpio-hog;
+ output-low;
+ gpios = <22 GPIO_ACTIVE_HIGH>;
+ line-name = "vdd_4p0_en";
+ };
+
uart1rs485 {
gpio-hog;
output-low;
diff --git a/arch/arm/dts/imx8mm-venice-gw7902.dts b/arch/arm/dts/imx8mm-venice-gw7902.dts
index 31f4c735fe4f..921bffae0cc9 100644
--- a/arch/arm/dts/imx8mm-venice-gw7902.dts
+++ b/arch/arm/dts/imx8mm-venice-gw7902.dts
@@ -261,7 +261,7 @@
&gpio1 {
gpio-line-names = "", "", "", "", "", "", "", "",
- "", "", "", "", "", "m2_reset", "", "m2_wdis#",
+ "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
@@ -283,7 +283,8 @@
&gpio4 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "",
- "", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485",
+ "lte_pwr#", "lte_rst", "lte_int", "",
+ "amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485",
"", "uart1_term", "uart1_half", "app_gpio2",
"mipi_gpio1", "", "", "";
};
@@ -738,14 +739,19 @@
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */
+ MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */
+ MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */
MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */
MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
+ MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
@@ -779,8 +785,6 @@
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
- MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
- MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
>;
};
diff --git a/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi b/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi
index 17e6828c79f8..10656ce903a5 100644
--- a/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi
@@ -6,6 +6,13 @@
#include "imx8mn-venice-u-boot.dtsi"
&gpio1 {
+ m2pwren {
+ gpio-hog;
+ output-low;
+ gpios = <8 GPIO_ACTIVE_HIGH>;
+ line-name = "m2_pwren";
+ };
+
m2rst {
gpio-hog;
output-low;
@@ -54,6 +61,13 @@
line-name = "app_gpio1";
};
+ vdd4p0en {
+ gpio-hog;
+ output-low;
+ gpios = <22 GPIO_ACTIVE_HIGH>;
+ line-name = "vdd_4p0_en";
+ };
+
uart1rs485 {
gpio-hog;
output-low;
diff --git a/arch/arm/dts/imx8mn-venice-gw7902.dts b/arch/arm/dts/imx8mn-venice-gw7902.dts
index dd4302ac1de4..029ccdbee7d5 100644
--- a/arch/arm/dts/imx8mn-venice-gw7902.dts
+++ b/arch/arm/dts/imx8mn-venice-gw7902.dts
@@ -256,7 +256,7 @@
&gpio1 {
gpio-line-names = "", "", "", "", "", "", "", "",
- "", "", "", "", "", "m2_reset", "", "m2_wdis#",
+ "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
@@ -278,7 +278,7 @@
&gpio4 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
- "", "", "", "", "", "app_gpio1", "", "uart1_rs485",
+ "", "", "", "", "", "app_gpio1", "vdd_4p0_en", "uart1_rs485",
"", "uart1_term", "uart1_half", "app_gpio2",
"mipi_gpio1", "", "", "";
};
@@ -689,10 +689,12 @@
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
+ MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */
MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
+ MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */
MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
@@ -726,8 +728,6 @@
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
- MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
- MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
>;
};
--
2.25.1
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