[PoC 147/241] global: Migrate CONFIG_PHY_INTERFACE_MODE to CFG

[Tom Rini]

Signed-off-by: Tom Rini <trini at konsulko.com>
---
 include/configs/socfpga_sr1500.h | 2 +-
 scripts/config_whitelist.txt     | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
index 432144cb40ce..70df27241ca6 100644
--- a/include/configs/socfpga_sr1500.h
+++ b/include/configs/socfpga_sr1500.h
@@ -11,7 +11,7 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SR1500 */
 
 /* Ethernet on SoC (EMAC) */
-#define CONFIG_PHY_INTERFACE_MODE	PHY_INTERFACE_MODE_RGMII
+#define CFG_PHY_INTERFACE_MODE	PHY_INTERFACE_MODE_RGMII
 /* The PHY is autodetected, so no MII PHY address is needed here */
 #define PHY_ANEG_TIMEOUT	8000
 
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 664b59d44050..9438ee6afdd7 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -156,7 +156,7 @@ CFG_PEN_ADDR_BIG_ENDIAN
 CFG_PHY_BASE_ADR
 CFG_PHY_ET1011C_TX_CLK_FIX
 CFG_PHY_ID
-CONFIG_PHY_INTERFACE_MODE
+CFG_PHY_INTERFACE_MODE
 CONFIG_PHY_IRAM_BASE
 CONFIG_PL011_CLOCK
 CONFIG_PL01x_PORTS
-- 
2.25.1