[PATCH] spi: zynqmp_gqspi: Update tapdelay value

[Dhruva Gole]

On 23/11/22 11:36, Ashok Reddy Soma wrote:
> From: T Karthik Reddy <t.karthik.reddy at xilinx.com>
> 
> Update GQSPI_LPBK_DLY_ADJ_DLY_1 tapdelay value for Versal for
> frequencies above 100MHz.
Please can you help me understand why this was needed to be updated?

If there was some bug/ anomally with 0x2 then can you describe why 
changing it to 0x1 helped?

or if it was wrongly written as 0x2 then I feel it's better to word the 
commit message as fix the GQSPI_LPBK_DLY_ADJ_DLY_1 tapdelay value for 
Versal as it was wrongly set to 0x2.

(something on those lines)

> 
> Signed-off-by: T Karthik Reddy <t.karthik.reddy at xilinx.com>
> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma at amd.com>
> ---
> 
>   drivers/spi/zynqmp_gqspi.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
> index 48eff777df..83a5c8aebf 100644
> --- a/drivers/spi/zynqmp_gqspi.c
> +++ b/drivers/spi/zynqmp_gqspi.c
> @@ -94,7 +94,7 @@
>   
>   #define GQSPI_BAUD_DIV_SHIFT		2
>   #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT	5
> -#define GQSPI_LPBK_DLY_ADJ_DLY_1	0x2
> +#define GQSPI_LPBK_DLY_ADJ_DLY_1	0x1
Was this always _intended_ to be 0x1 but was wrongly set to 0x2
or is this some new development that is changing this value to 0x1 from 0x2?
>   #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT	3
>   #define GQSPI_LPBK_DLY_ADJ_DLY_0	0x3
>   #define GQSPI_USE_DATA_DLY		0x1

-- 
Thanks and Regards,
Dhruva Gole