[PATCH 1/2] arm: socfpga: soc64: Add mask support when enable/disable bridges

Jit Loon Lim jit.loon.lim at intel.com
Wed Nov 23 15:07:19 CET 2022


From: Ley Foon Tan <ley.foon.tan at intel.com>

HSD #18016042797-1: The existing ignore the "mask" value when call to socfpga_bridges_reset().

This patch add the mask support when bridge enable/disable.

Mask value:
BIT0: soc2fpga
BIT1: lwhps2fpga
BIT2: fpga2soc

These bridges available only in Stratix 10:
BIT3: f2sdram0
BIT4: f2sdram1
BIT5: f2sdram2

Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim at intel.com>
---
 .../include/mach/reset_manager_soc64.h        |   9 +-
 arch/arm/mach-socfpga/misc_soc64.c            |   2 +-
 arch/arm/mach-socfpga/reset_manager_s10.c     | 154 +++++++++++-------
 3 files changed, 101 insertions(+), 64 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
index 9589b61749..b662b4450d 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
@@ -9,7 +9,8 @@
 void reset_deassert_peripherals_handoff(void);
 int cpu_has_been_warmreset(void);
 void print_reset_info(void);
-void socfpga_bridges_reset(int enable);
+void socfpga_bridges_reset(int enable, unsigned int mask);
+void socfpga_bridges_reset_psci(int enable, unsigned int mask);
 
 #define RSTMGR_SOC64_STATUS	0x00
 #define RSTMGR_SOC64_HDSKEN	0x10
@@ -29,12 +30,6 @@ void socfpga_bridges_reset(int enable);
 #define RSTMGR_BRGMODRST_F2SDRAM1_MASK	BIT(4)
 #define RSTMGR_BRGMODRST_F2SDRAM2_MASK	BIT(5)
 #define RSTMGR_BRGMODRST_DDRSCH_MASK	BIT(6)
-#define BRGMODRST_SOC2FPGA_BRIDGES	(RSTMGR_BRGMODRST_SOC2FPGA_MASK | \
-					 RSTMGR_BRGMODRST_LWSOC2FPGA_MASK)
-#define BRGMODRST_FPGA2SOC_BRIDGES	(RSTMGR_BRGMODRST_FPGA2SOC_MASK | \
-					 RSTMGR_BRGMODRST_F2SDRAM0_MASK | \
-					 RSTMGR_BRGMODRST_F2SDRAM1_MASK | \
-					 RSTMGR_BRGMODRST_F2SDRAM2_MASK)
 
 #define RSTMGR_HDSKEN_FPGAHSEN		BIT(2)
 #define RSTMGR_HDSKREQ_FPGAHSREQ	BIT(2)
diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c
index 2acdfad07b..49b241b7b8 100644
--- a/arch/arm/mach-socfpga/misc_soc64.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -87,5 +87,5 @@ void do_bridge_reset(int enable, unsigned int mask)
 		return;
 	}
 
-	socfpga_bridges_reset(enable);
+	socfpga_bridges_reset(enable, mask);
 }
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index 0274c4dbdb..128cdbbbe3 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -24,30 +24,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define F2SDRAM_SIDEBAND_FLAGOUTSET0	0x50
 #define F2SDRAM_SIDEBAND_FLAGOUTCLR0	0x54
 
-#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
-#define FLAGINSTATUS0_MPFE_NOC_IDLE	(BIT(0) | BIT(4) | BIT(8))
-#define FLAGINSTATUS0_MPFE_NOC_IDLEACK	(BIT(1) | BIT(5) | BIT(9))
-#define FLAGINSTATUS0_F2S_CMD_EMPTY	(BIT(2) | BIT(6) | BIT(10))
-#define FLAGINSTATUS0_F2S_RESP_EMPTY	(BIT(3) | BIT(7) | BIT(11))
-
-#define FLGAOUTSET0_MPFE_NOC_IDLEREQ	(BIT(0) | BIT(3) | BIT(6))
-#define FLGAOUTSET0_F2S_EN		(BIT(1) | BIT(4) | BIT(7))
-#define FLGAOUTSET0_F2S_FORCE_DRAIN	(BIT(2) | BIT(5) | BIT(8))
-
-#define FLGAOUTCLR0_F2S_IDLEREQ		(BIT(0) | BIT(3) | BIT(6))
-#else
-#define FLAGINSTATUS0_MPFE_NOC_IDLE	BIT(0)
-#define FLAGINSTATUS0_MPFE_NOC_IDLEACK	BIT(1)
-#define FLAGINSTATUS0_F2S_CMD_EMPTY	BIT(2)
-#define FLAGINSTATUS0_F2S_RESP_EMPTY	BIT(3)
-
-#define FLGAOUTSET0_MPFE_NOC_IDLEREQ	BIT(0)
-#define FLGAOUTSET0_F2S_EN		BIT(1)
-#define FLGAOUTSET0_F2S_FORCE_DRAIN	BIT(2)
-
-#define FLGAOUTCLR0_F2S_IDLEREQ		BIT(0)
-#endif
-
 #define POLL_FOR_ZERO(expr, timeout_ms)		\
 	{					\
 		int timeout = (timeout_ms);	\
@@ -110,26 +86,79 @@ void socfpga_per_reset_all(void)
 	writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST);
 }
 
-static __always_inline void socfpga_f2s_bridges_reset(int enable)
+static __always_inline void socfpga_f2s_bridges_reset(int enable,
+						      unsigned int mask)
 {
 	int timeout_ms = 300;
 	u32 empty;
+	u32 brg_mask;
+	u32 flagout_idlereq = 0;
+	u32 flagoutset_fdrain = 0;
+	u32 flagoutset_en = 0;
+	u32 flaginstatus_idleack = 0;
+	u32 flaginstatus_respempty = 0;
+
+	if (CONFIG_IS_ENABLED(TARGET_SOCFPGA_STRATIX10)) {
+		/* Support fpga2soc and f2sdram */
+		brg_mask = mask & (RSTMGR_BRGMODRST_FPGA2SOC_MASK |
+				   RSTMGR_BRGMODRST_F2SDRAM0_MASK |
+				   RSTMGR_BRGMODRST_F2SDRAM1_MASK |
+				   RSTMGR_BRGMODRST_F2SDRAM2_MASK);
+
+		if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM0_MASK) {
+			flagout_idlereq |= BIT(0);
+			flaginstatus_idleack |= BIT(1);
+			flagoutset_fdrain |= BIT(2);
+			flagoutset_en |= BIT(1);
+			flaginstatus_respempty |= BIT(3);
+		}
+
+		if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM1_MASK) {
+			flagout_idlereq |= BIT(3);
+			flaginstatus_idleack |= BIT(5);
+			flagoutset_fdrain |= BIT(5);
+			flagoutset_en |= BIT(4);
+			flaginstatus_respempty |= BIT(7);
+		}
+
+		if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM2_MASK) {
+			flagout_idlereq |= BIT(6);
+			flaginstatus_idleack |= BIT(9);
+			flagoutset_fdrain |= BIT(8);
+			flagoutset_en |= BIT(7);
+			flaginstatus_respempty |= BIT(11);
+		}
+	} else {
+		/* Support fpga2soc only */
+		brg_mask = mask & RSTMGR_BRGMODRST_FPGA2SOC_MASK;
+		if (brg_mask & RSTMGR_BRGMODRST_FPGA2SOC_MASK) {
+			flagout_idlereq |= BIT(0);
+			flaginstatus_idleack |= BIT(1);
+			flagoutset_fdrain |= BIT(2);
+			flagoutset_en |= BIT(1);
+			flaginstatus_respempty |= BIT(3);
+		}
+	}
+
+	/* mask is not set, return here */
+	if (!brg_mask)
+		return;
 
 	if (enable) {
 		clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
-			     BRGMODRST_FPGA2SOC_BRIDGES);
+			     brg_mask);
 		clrbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +
 			     F2SDRAM_SIDEBAND_FLAGOUTSET0,
-			     FLGAOUTSET0_MPFE_NOC_IDLEREQ);
+			     flagout_idlereq);
 
 		POLL_FOR_ZERO((readl(SOCFPGA_F2SDRAM_MGR_ADDRESS +
 			      F2SDRAM_SIDEBAND_FLAGINSTATUS0) &
-			      FLAGINSTATUS0_MPFE_NOC_IDLEACK), timeout_ms);
+			      flaginstatus_idleack), timeout_ms);
 		clrbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +
 			     F2SDRAM_SIDEBAND_FLAGOUTSET0,
-			     FLGAOUTSET0_F2S_FORCE_DRAIN);
+			     flagoutset_fdrain);
 		setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +
-			     F2SDRAM_SIDEBAND_FLAGOUTSET0, FLGAOUTSET0_F2S_EN);
+			     F2SDRAM_SIDEBAND_FLAGOUTSET0, flagoutset_en);
 
 		__socfpga_udelay(1); /* wait 1us */
 	} else {
@@ -140,11 +169,11 @@ static __always_inline void socfpga_f2s_bridges_reset(int enable)
 		POLL_FOR_SET(readl(socfpga_get_rstmgr_addr() +
 			     RSTMGR_SOC64_HDSKACK), timeout_ms);
 		clrbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +
-			     F2SDRAM_SIDEBAND_FLAGOUTSET0, FLGAOUTSET0_F2S_EN);
+			     F2SDRAM_SIDEBAND_FLAGOUTSET0, flagoutset_en);
 		__socfpga_udelay(1);
 		setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +
 			     F2SDRAM_SIDEBAND_FLAGOUTSET0,
-			     FLGAOUTSET0_F2S_FORCE_DRAIN);
+			     flagoutset_fdrain);
 		__socfpga_udelay(1);
 
 		do {
@@ -154,11 +183,11 @@ static __always_inline void socfpga_f2s_bridges_reset(int enable)
 			 */
 			empty = readl(SOCFPGA_F2SDRAM_MGR_ADDRESS +
 				      F2SDRAM_SIDEBAND_FLAGINSTATUS0) &
-				      FLAGINSTATUS0_F2S_RESP_EMPTY;
+				      flaginstatus_respempty;
 			if (empty) {
 				empty = readl(SOCFPGA_F2SDRAM_MGR_ADDRESS +
 					      F2SDRAM_SIDEBAND_FLAGINSTATUS0) &
-					      FLAGINSTATUS0_F2S_RESP_EMPTY;
+					      flaginstatus_respempty;
 				if (empty)
 					break;
 			}
@@ -168,60 +197,73 @@ static __always_inline void socfpga_f2s_bridges_reset(int enable)
 		} while (timeout_ms);
 
 		setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
-			     BRGMODRST_FPGA2SOC_BRIDGES &
-			     ~RSTMGR_BRGMODRST_FPGA2SOC_MASK);
+			     brg_mask & ~RSTMGR_BRGMODRST_FPGA2SOC_MASK);
 		clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKREQ,
 			     RSTMGR_HDSKREQ_FPGAHSREQ);
 		setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +
 			     F2SDRAM_SIDEBAND_FLAGOUTCLR0,
-			     FLGAOUTCLR0_F2S_IDLEREQ);
+			     flagout_idlereq);
 	}
 }
 
-static __always_inline void socfpga_s2f_bridges_reset(int enable)
+static __always_inline void socfpga_s2f_bridges_reset(int enable,
+						      unsigned int mask)
 {
+	unsigned int noc_mask = 0;
+	unsigned int brg_mask = 0;
+
+	if (mask & RSTMGR_BRGMODRST_SOC2FPGA_MASK) {
+		noc_mask = SYSMGR_NOC_H2F_MSK;
+		brg_mask = RSTMGR_BRGMODRST_SOC2FPGA_MASK;
+	}
+
+	if (mask & RSTMGR_BRGMODRST_LWSOC2FPGA_MASK) {
+		noc_mask |= SYSMGR_NOC_LWH2F_MSK;
+		brg_mask |= RSTMGR_BRGMODRST_LWSOC2FPGA_MASK;
+	}
+
+	/* s2f mask is not set, return here */
+	if (!brg_mask)
+		return;
+
 	if (enable) {
 		/* clear idle request to all bridges */
 		setbits_le32(socfpga_get_sysmgr_addr() +
-			     SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0);
+			     SYSMGR_SOC64_NOC_IDLEREQ_CLR, noc_mask);
 
 		/* Release SOC2FPGA bridges from reset state */
 		clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
-			     BRGMODRST_SOC2FPGA_BRIDGES);
+			      brg_mask);
 
 		/* Poll until all idleack to 0 */
 		POLL_FOR_ZERO(readl(socfpga_get_sysmgr_addr() +
 			      SYSMGR_SOC64_NOC_IDLEACK), 300);
 	} else {
 		/* set idle request to all bridges */
-		writel(~0,
-		       socfpga_get_sysmgr_addr() +
-		       SYSMGR_SOC64_NOC_IDLEREQ_SET);
+		setbits_le32(socfpga_get_sysmgr_addr() +
+			     SYSMGR_SOC64_NOC_IDLEREQ_SET, noc_mask);
 
 		/* Enable the NOC timeout */
 		writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
 
 		/* Poll until all idleack to 1 */
 		POLL_FOR_ZERO(readl(socfpga_get_sysmgr_addr() +
-				    SYSMGR_SOC64_NOC_IDLEACK) ^
-			      (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK),
-			      300);
+				     SYSMGR_SOC64_NOC_IDLEACK) ^ noc_mask, 300);
 
 		POLL_FOR_ZERO(readl(socfpga_get_sysmgr_addr() +
-				    SYSMGR_SOC64_NOC_IDLESTATUS) ^
-			      (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK),
+				    SYSMGR_SOC64_NOC_IDLESTATUS) ^ noc_mask,
 			      300);
 
-		/* Reset all SOC2FPGA bridges (except NOR DDR scheduler & F2S) */
+		/* Reset SOC2FPGA bridges */
 		setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
-			     BRGMODRST_SOC2FPGA_BRIDGES);
+			     brg_mask);
 
 		/* Disable NOC timeout */
 		writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
 	}
 }
 
-void socfpga_bridges_reset(int enable)
+void socfpga_bridges_reset(int enable, unsigned int mask)
 {
 	if (!IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) {
 		u64 arg = enable;
@@ -233,15 +275,15 @@ void socfpga_bridges_reset(int enable)
 			printf("Failed to %s the HPS bridges, error %d\n",
 			       enable ? "enable" : "disable", ret);
 	} else {
-		socfpga_s2f_bridges_reset(enable);
-		socfpga_f2s_bridges_reset(enable);
+		socfpga_s2f_bridges_reset(enable, mask);
+		socfpga_f2s_bridges_reset(enable, mask);
 	}
 }
 
-void __secure socfpga_bridges_reset_psci(int enable)
+void __secure socfpga_bridges_reset_psci(int enable, unsigned int mask)
 {
-	socfpga_s2f_bridges_reset(enable);
-	socfpga_f2s_bridges_reset(enable);
+	socfpga_s2f_bridges_reset(enable, mask);
+	socfpga_f2s_bridges_reset(enable, mask);
 }
 
 /*
-- 
2.26.2



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