[PATCH 2/3] ram: ast2600: Improve ddr4 timing and signal quality

[Tom Rini]

On Fri, Nov 11, 2022 at 03:30:07PM +0800, Dylan Hung wrote:

> Adjust the following settings to get better timing and signal quality.
> 
> 1. write DQS/DQ delay
> - 1e6e2304[0]
> - 1e6e2304[15:8]
> 
> 2. read DQS/DQ delay
> - 0x1e6e0298[0]
> - 0x1e6e0298[15:8]
> 
> 3. CLK/CA timing
> - 0x1e6e01a8[31]
> 
> 4. Read and write termination
> - change RTT_ROM from 40 ohm to 48 ohm (MR1[10:8])
> - change RTT_PARK from disable to 48 ohm (MR5[8:6])
> - change RTT_WR from 120 ohm to disable (MR2[11:9])
> - change PHY ODT from 40 ohm to 80 ohm (0x1e6e0130[10:8])
> 
> Note1: Both DDR-PHY and DDR controller have their own registers for DDR4
> Mode Registers (MR0~MR6).  This patch introduces macros to synchronize
> the MR value on both sides.
> 
> Note2: the waveform meansurement can be found in item #21 of Aspeed
> AST26x0 Application note (AP note).
> 
> Signed-off-by: Dylan Hung <dylan_hung at aspeedtech.com>

Applied to u-boot/master, thanks!

-- 
Tom
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