Testing v2022.10-rc5 on mt7621

Sven F. sven.falempin at gmail.com
Mon Oct 3 19:08:43 CEST 2022


Following up on request about helping to test mt7621

On Wed, Sep 21, 2022 at 11:13 AM Sven F. <sven.falempin at gmail.com> wrote:

> Dear readers,
>
> I have a mt7621 spi nor with 256MB DDR board,
> and I am trying to get an open source software suite on it.
>
> IE : u-boot 2022.10 and open wrt v22.03.0
>
> I follow instruction and build u-boot with :
>
> export CROSS_COMPILE=mipsel-linux-gnu-
> make mrproper && make O=build mt7621_rfb_defconfig && \
> make O=build -j$(nproc) 2>&1 | tee ../uboot.build.log.mt7621_rfb_defconfig
>
> The output file looks ok but the last part of LZMA is not recognized fully.
>
> $ binwalk ./build/u-boot-mt7621.bin
>
> DECIMAL       HEXADECIMAL     DESCRIPTION
>
> --------------------------------------------------------------------------------
> 2156          0x86C           uImage header, header size: 64 bytes, header
> CRC: 0x3D774D5C, created: 2022-09-21 13:56:55, image size: 3
> 8828 bytes, Data Address: 0x80100000, Entry Point: 0x80100000, data CRC:
> 0x38979001, OS: Firmware, CPU: MIPS, \
> image type: Standalone Program, compression type: none, image name:
> "MT7621 U-Boot SPL"
> 41048         0xA058          uImage header, header size: 64 bytes, header
> CRC: 0x18B75518, created: 2022-09-21 13:56:49, image size: 1
> 45331 bytes, Data Address: 0x80200000, Entry Point: 0x80200000, data CRC:
> 0xB39FB0D8, OS: Firmware, CPU: MIPS, \
> image type: Standalone Program, compression type: lzma, image name:
> "U-Boot 2022.10-rc4 for mt7621 bo"
> 41112         0xA098          LZMA compressed data, properties: 0x5D,
> dictionary size: 67108864 bytes, uncompressed size: -1 bytes
>
> Remark on the build process, only one warning:
>
> /home/toor/2022/official/bootloader/u-boot/build/../scripts/dtc/pylibfdt/setup.py:21
> DeprecationWarning: \
> The distutils package is deprecated and slated for removal in Python 3.12.
> Use setuptools or check PEP 632 for potential alternatives
>
> I think it would sensible to put some checksum of the online binaries file
> for the `DDR initialization binary blob`
>
> + 1dda68aa089f0ff262e01539b990dea478952e9fb68bcc0a8cd6f76f0135c62e
> ./mt7621_stage_sram.bin
> + 8ee419275144fc298e9444d413d98e965a55d283152a74ea6a1f8de79eb516b6
> ./mt7621_stage_sram_noprint.bin
>
> and the CROSS_COMPILE define may be signal `mipsel-linux-gnu-`
>
> in
> https://github.com/u-boot/u-boot/blob/master/doc/board/mediatek/mt7621.rst
>
> Before burning the ROM , I would like to validate the build somehow since
> it is very hard to recover from a bad bootloader !
> `Burn the u-boot-mt7621.bin to the SPI-NOR` is a bit drastic.
>
> Is it possible to boot one of those from memory using the `go` command to
> check if the build looks ok
>
> 1990a6e661e450d944ff69c103cb0ca7  ./build/u-boot-dtb.img
> 1990a6e661e450d944ff69c103cb0ca7  ./build/u-boot.img
> d025641feb8aeb423c5bb829a989ddd4  ./build/u-boot-lzma.img
> 27b67fb29c11ea542405e25829df00ee  ./build/u-boot-spl-ddr.img
> 0c7d7fa983b3e7b7c9cd202e89f6cb07  ./build/mt7621_stage_sram.bin
> d1ee76fe3750386e4ec5de3cb0599c8f  ./build/u-boot.bin
> d1ee76fe3750386e4ec5de3cb0599c8f  ./build/u-boot-dtb.bin
> be651a79adc284ee3aac5edfc873eacc  ./build/u-boot-mt7621.bin
> 6fa3b83a89174c828b4af8c53beeece6  ./build/u-boot-nodtb.bin
> d7d4fd33c9c2bdeeb074d3367b09cf10  ./build/u-boot-spl-ddr.bin
> 980971dba7452050a975398324d771e1  ./build/u-boot
>
> Is it possible to do something similar ? please advice
>
> => bootp 0x80010000 u-boot-nodtb.bin
> => go 0x80010000
>
> Thank you for reading that far.
>
> PS: some board data.
>
>
>
> => bdinfo
> boot_params = 0x8FEB1160
> memstart    = 0x80000000
> memsize     = 0x10000000
> flashstart  = 0x00000000
> flashsize   = 0x00000000
> flashoffset = 0x00000000
> ethaddr     = (not set)
> IP addr     = 192.168.1.
> baudrate    = 115200 bps
> relocaddr   = 0x8FFB0000
> reloc off   = 0x0FDB0000
>
> >> Initializing DDR3
>
> >> Applying AC timing parameters (try 1)
> Expected DRAM size: 128MB
>
> >> Setting DDR/CPU PLL ...
> Using 3PLL mode with External loopback
> DDR/CPU clock will be set to 1200MHz/880MHz
>
> >> Starting DDR PLL calibration ...
> DDR PLL2/3/4 feedback delay: 23/13/18
> DDR 3PLL mode calibration passed
>
> >> Starting DQS Gating Window Delay calibration
>          0   8  16  24  32  40  48  56  64  72  80  88  96 104 112 120
>       ----------------------------------------------------------------
> 0000:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0001:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0002:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0003:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0004:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0005:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0006:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0007:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0008:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0009:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 000A:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 000B:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 000C:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 000D:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 000E:|   0   0   0   0   0   0   0   0   0   0   1   1   0   1   1   1
> 000F:|   0   0   0   0   0   1   1   0   1   1   1   0   1   1   0   0
> 0010:|   1   1   1   1   1   0   1   1   1   1   0   0   0   0   0   0
> 0011:|   1   1   0   1   0   0   0   0   0   0   0   0   0   0   0   0
> 0012:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0013:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0014:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0015:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0016:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0017:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0018:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0019:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 001A:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 001B:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 001C:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 001D:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 001E:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 001F:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> Found coarse/fine delay value: 16/32
>
> >> Starting DLE calibration
>          0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15
>       ----------------------------------------------------------------
> 0000:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> Failed to find optimal DQS factor
>
> >> Got DRAM size 0MB
> Retrying ...
>
> >> Applying AC timing parameters (try 2)
> Expected DRAM size: 256MB
>
> >> Setting DDR/CPU PLL ...
> Using 3PLL mode with External loopback
> DDR/CPU clock will be set to 1200MHz/880MHz
>
> >> Starting DDR PLL calibration ...
> DDR PLL2/3/4 feedback delay: 23/13/18
> DDR 3PLL mode calibration passed
>
> >> Starting DQS Gating Window Delay calibration
>          0   8  16  24  32  40  48  56  64  72  80  88  96 104 112 120
>       ----------------------------------------------------------------
> 0000:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0001:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0002:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0003:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0004:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0005:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0006:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0007:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0008:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0009:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 000A:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 000B:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 000C:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 000D:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 000E:|   0   0   0   0   0   0   0   0   0   0   1   1   1   1   1   1
> 000F:|   0   0   0   0   0   1   1   1   1   1   1   1   1   1   1   0
> 0010:|   1   1   1   1   1   1   1   1   1   0   0   0   0   0   0   0
> 0011:|   1   1   1   1   1   0   0   0   0   0   0   0   0   0   0   0
> 0012:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0013:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0014:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0015:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0016:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0017:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0018:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 0019:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 001A:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 001B:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 001C:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 001D:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 001E:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> 001F:|   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0
> Found coarse/fine delay value: 15/80
>
> >> Starting DLE calibration
>          0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15
>       ----------------------------------------------------------------
> 0000:|   0   0   0   0   0   0   0   0   1   1   1   0   0   0   0   0
> Optimal DQS factor: 9
>
> >> Starting RX DQ per-bit delay calibration
> Bit      0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15
>       ----------------------------------------------------------------
> Delay   11  11  11  12   9  11   9   9   7   7   9   8   9  10   8  10
>
> >> Starting DQS delay calibration
> Bit ( Range ) Center
> --------------------
>   0 (  1~ 62)     31
>   1 (  1~ 61)     31
>   2 (  1~ 60)     30
>   3 (  1~ 62)     31
>   4 (  0~ 62)     31
>   5 (  1~ 63)     32
>   6 (  1~ 61)     31
>   7 (  1~ 63)     32
> DQS0 input delay: 32
>
> Bit ( Range ) Center
> --------------------
>   8 (  1~ 59)     30
>   9 (  1~ 58)     29
>  10 (  1~ 59)     30
>  11 (  1~ 58)     29
>  12 (  2~ 60)     31
>  13 (  1~ 59)     30
>  14 (  1~ 59)     30
>  15 (  1~ 60)     30
> DQS1 input delay: 31
>
> >> Final DQ delay value
> Bit      0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15
>       ----------------------------------------------------------------
> Delay   12  12  13  13  10  11  10   9   8   9  10  10   9  11   9  11
>
> >> Starting TX DQ/QDS per-byte calibration
> Byte 0: (DQS,DQ)=(8,8)
> Byte 1: (DQS,DQ)=(8,8)
>
> DDR calibration passed
>
> >> Got DRAM size 256MB
>
> DRAM initialization succeeded
>
>
> U-Boot SPL 2018.09-svn35 (Mar 11 2021 - 19:17:36 +0800)
> Trying to boot from NOR
>
>
> U-Boot 2018.09-svn35 (Mar 11 2021 - 19:17:36 +0800)
>
> CPU:   MediaTek MT7621AT ver 1, eco 3
> Clocks: CPU: 880MHz, DDR: 1200MHz, Bus: 220MHz, XTAL: 40MHz
> Model: MediaTek MT7621 reference board
> DRAM:  256 MiB
> Loading Environment from SPI Flash... SF: Detected w25q128bv with page
> size 256 Bytes, erase size 64 KiB, total 16 MiB
> *** Warning - bad CRC, using default environment
>
> In:    uartlite0 at 1e000c00
> Out:   uartlite0 at 1e000c00
> Err:   uartlite0 at 1e000c00
> Net:
> Warning: eth at 1e100000 (eth0) using random MAC address - 5e:69:c8:f8:cf:5b
> eth0: eth at 1e100000
> Hit any key to stop autoboot:  0
>
>   *** U-Boot Boot Menu ***
>
>      1. Startup system (Default)
>      2. Upgrade firmware
>      3. Upgrade bootloader
>      4. Upgrade bootloader (advanced mode)
>      5. Load image
>      0. U-Boot console
>
>
>


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