[PATCH v4 3/3] riscv: Fix build against binutils 2.38

[Tom Rini]

On Mon, Oct 03, 2022 at 06:07:54PM +0200, Heinrich Schuchardt wrote:

> From: Alexandre Ghiti <alexandre.ghiti at canonical.com>
> 
> The following description is copied from the equivalent patch for the
> Linux Kernel proposed by Aurelien Jarno:
> 
> >From version 2.38, binutils default to ISA spec version 20191213. This
> means that the csr read/write (csrr*/csrw*) instructions and fence.i
> instruction has separated from the `I` extension, become two standalone
> extensions: Zicsr and Zifencei. As the kernel uses those instruction,
> this causes the following build failure:
> 
> arch/riscv/cpu/mtrap.S: Assembler messages:
> arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
> arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
> arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
> arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
> 
> Signed-off-by: Alexandre Ghiti <alexandre.ghiti at canonical.com>
> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
> Tested-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
> Tested-by: Heiko Stuebner <heiko at sntech.de>
> Tested-by: Christian Stewart <christian at paral.in>
> Reviewed-by: Rick Chen <rick at andestech.com>

Applied to u-boot/master, thanks!

-- 
Tom
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