[PATCH v5 2/3] arch/riscv: add semihosting support for RISC-V

[Rick Chen]

> From: Kautuk Consul <kconsul at ventanamicro.com>
> Sent: Friday, September 23, 2022 3:03 PM
> To: Rayagonda Kokatanur <rayagonda.kokatanur at broadcom.com>; Sean Anderson <sean.anderson at seco.com>; Rick Jian-Zhi Chen(陳建志) <rick at andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang at andestech.com>; Bin Meng <bmeng.cn at gmail.com>; Simon Glass <sjg at chromium.org>; Ilias Apalodimas <ilias.apalodimas at linaro.org>; Alexandru Gagniuc <mr.nuke.me at gmail.com>; Philippe Reynes <philippe.reynes at softathome.com>; Heinrich Schuchardt <xypron.glpk at gmx.de>; Rasmus Villemoes <rasmus.villemoes at prevas.dk>; Eugen Hristev <eugen.hristev at microchip.com>; Stefan Roese <sr at denx.de>; Loic Poulain <loic.poulain at linaro.org>; Peng Fan <peng.fan at nxp.com>; Michal Simek <michal.simek at amd.com>
> Cc: u-boot at lists.denx.de; Kautuk Consul <kconsul at ventanamicro.com>; Anup Patel <apatel at ventanamicro.com>
> Subject: [PATCH v5 2/3] arch/riscv: add semihosting support for RISC-V
>
> We add RISC-V semihosting based serial console for JTAG based early debugging.
>
> The RISC-V semihosting specification is available at:
> https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
>
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> Signed-off-by: Kautuk Consul <kconsul at ventanamicro.com>
> ---
>  arch/riscv/include/asm/spl.h |  1 +
>  arch/riscv/lib/Makefile      |  2 ++
>  arch/riscv/lib/interrupts.c  | 25 +++++++++++++++++++++++++  arch/riscv/lib/semihosting.c | 24 ++++++++++++++++++++++++
>  lib/Kconfig                  | 10 +++++-----
>  5 files changed, 57 insertions(+), 5 deletions(-)  create mode 100644 arch/riscv/lib/semihosting.c

Reviewed-by: Rick Chen <rick at andestech.com>