[PATCH 1/1] imx8m: ddr_init: fix reading of DDR4 MR registers

[Ying-Chun Liu (PaulLiu)]

Accorting to commit 290ffe57886271a6 we need to read more significant
bytes to get a non-zero value. However commit 7e9bd84883aeb1e2 removes
it by accident. Thus we add the changes back. This is needed to let
imx8mm-cl-iot-gate to boot correctly.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
Cc: Fabio Estevam <festevam at denx.de>
Cc: Marek Vasut <marex at denx.de>
Cc: Peng Fan <peng.fan at nxp.com>
Cc: Rasmus Villemoes <rasmus.villemoes at prevas.dk>
Cc: Stefano Babic <sbabic at denx.de>
Cc: NXP i.MX U-Boot Team <uboot-imx at nxp.com>
---
 drivers/ddr/imx/imx8m/ddr_init.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c
index d964184ddc..7a683b1d36 100644
--- a/drivers/ddr/imx/imx8m/ddr_init.c
+++ b/drivers/ddr/imx/imx8m/ddr_init.c
@@ -134,8 +134,14 @@ unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
 		tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
 	} while ((tmp & 0x8) == 0);
 	tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
-	tmp = tmp & 0xff;
 	reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
+	while (tmp) { // try to find a significant byte in the word
+		if (tmp & 0xff) {
+			tmp &= 0xff;
+			break;
+		}
+		tmp >>= 8;
+	}
 
 	return tmp;
 }
-- 
2.35.1