[PATCH v2 2/4] riscv: dts: Add QSPI NAND device node

Conor Dooley conor at kernel.org
Sat Oct 22 13:27:52 CEST 2022


On Fri, Oct 21, 2022 at 12:29:20PM +0530, Padmarao Begari wrote:
> Add QSPI NAND device node to the Microchip PolarFire SoC
> Icicle kit device tree.
> 
> The Winbond NAND flash memory can be connected to the
> Icicle Kit by using the Mikroe Flash 5 click board and
> the Pi 3 Click shield.
> 
> Signed-off-by: Padmarao Begari <padmarao.begari at microchip.com>
> ---
>  arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> index 876c475069..e1fbedc507 100644
> --- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> @@ -18,6 +18,7 @@
>  	aliases {
>  		serial1 = &uart1;
>  		ethernet0 = &mac1;
> +		spi0 = &qspi;
>  	};
>  
>  	chosen {
> @@ -113,3 +114,17 @@
>  		ti,fifo-depth = <0x1>;
>  	};
>  };
> +
> +&qspi {
> +	status = "okay";
> +	num-cs = <1>;

Convention suggests a blank line before children, right?
Other than that, LGTM..
Reviewed-by: Conor Dooley <conor.dooley at microchip.com>

> +	flash0: flash at 0 {
> +		compatible = "spi-nand";
> +		reg = <0x0>;
> +		spi-tx-bus-width = <4>;
> +		spi-rx-bus-width = <4>;
> +		spi-max-frequency = <20000000>;
> +		spi-cpol;
> +		spi-cpha;
> +	};
> +};
> -- 
> 2.25.1
> 


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