[PATCH v5 2/5] ARM: imx: imx8mp: Enable support for i2c5 and i2c6 on i.MX8MP

[Peng Fan]

On 10/25/2022 5:54 PM, Martyn Welch wrote:
> The i.MX8MP SoC contains 2 more i2c buses. Add support for the
> configuration of these buses.
> 
> Signed-off-by: Martyn Welch <martyn.welch at collabora.com>
> ---
> 
> Changes in v2:
>   - None
> 
> Changes in v3:
>   - None
> 
> Changes in v4:
>   - None
> 
> Changes in v5:
>   - None
> 
>   arch/arm/include/asm/arch-imx8m/imx-regs.h |  4 ++++
>   arch/arm/mach-imx/i2c-mxv7.c               |  6 ++++++
>   arch/arm/mach-imx/imx8m/clock_imx8mm.c     | 12 +++++++++---
>   3 files changed, 19 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
> index c46d4f7e00..6595d97f0a 100644
> --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
> +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
> @@ -44,6 +44,10 @@
>   #define I2C3_BASE_ADDR		0x30A40000
>   #define I2C4_BASE_ADDR		0x30A50000
>   #define UART4_BASE_ADDR		0x30A60000
> +#ifdef CONFIG_IMX8MP
> +#define I2C5_BASE_ADDR          0x30AD0000
> +#define I2C6_BASE_ADDR          0x30AE0000
> +#endif
>   #define USDHC1_BASE_ADDR	0x30B40000
>   #define USDHC2_BASE_ADDR	0x30B50000
>   #define QSPI0_AMBA_BASE     0x08000000
> diff --git a/arch/arm/mach-imx/i2c-mxv7.c b/arch/arm/mach-imx/i2c-mxv7.c
> index 85d648b56e..a5866cf9f7 100644
> --- a/arch/arm/mach-imx/i2c-mxv7.c
> +++ b/arch/arm/mach-imx/i2c-mxv7.c
> @@ -70,6 +70,12 @@ static void * const i2c_bases[] = {
>   #ifdef I2C4_BASE_ADDR
>   	(void *)I2C4_BASE_ADDR,
>   #endif
> +#ifdef I2C5_BASE_ADDR
> +	(void *)I2C5_BASE_ADDR,
> +#endif
> +#ifdef I2C6_BASE_ADDR
> +	(void *)I2C6_BASE_ADDR,
> +#endif
>   };
>   
>   /* i2c_index can be from 0 - 3 */
> diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> index 4db55f8608..64ad57e9b3 100644
> --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> @@ -36,11 +36,17 @@ void enable_ocotp_clk(unsigned char enable)
>   
>   int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
>   {
> -	/* 0 - 3 is valid i2c num */
> -	if (i2c_num > 3)
> +	u8 i2c_ccgr[6] = {
> +			CCGR_I2C1, CCGR_I2C2, CCGR_I2C3, CCGR_I2C4,
> +#if (IS_ENABLED(CONFIG_IMX8MP))
> +			CCGR_I2C5_8MP, CCGR_I2C6_8MP
> +#endif
> +	};
> +
> +	if (i2c_num > ARRAY_SIZE(i2c_ccgr))
>   		return -EINVAL;
>   
> -	clock_enable(CCGR_I2C1 + i2c_num, !!enable);
> +	clock_enable(i2c_ccgr[i2c_num], !!enable);
>   
>   	return 0;
>   }

With DM_CLK or SPL_DM_CLK enabled, this function is not needed anymore.
Do you have DM_CLK and SPL_DM_CLK enabled?

Regards,
Peng.