[PATCH v3 1/4] riscv: dts: Update memory configuration

[Rick Chen]

> From: Padmarao Begari <padmarao.begari at microchip.com>
> Sent: Thursday, October 27, 2022 2:02 PM
> To: u-boot at lists.denx.de; jagan at amarulasolutions.com; Rick Jian-Zhi Chen(陳建志) <rick at andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang at andestech.com>; bmeng.cn at gmail.com
> Cc: cyril.jean at microchip.com; conor.dooley at microchip.com; valentina.fernandezalanis at microchip.com; nagasuresh.relli at microchip.com; Padmarao Begari <padmarao.begari at microchip.com>
> Subject: [PATCH v3 1/4] riscv: dts: Update memory configuration
>
> In the v2022.10 Icicle reference design, the seg registers have been changed, resulting in a required change to the memory map.
> A small 4MB reservation is made at the end of 32-bit DDR to provide some memory for the HSS to use, so that it can cache its payload between reboots of a specific context.
>
> Co-developed-by: Conor Dooley <conor.dooley at microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> Signed-off-by: Padmarao Begari <padmarao.begari at microchip.com>
> Reviewed-by: Conor Dooley <conor.dooley at microchip.com>
> ---
>  arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 75 +++++---------------
>  1 file changed, 17 insertions(+), 58 deletions(-)

Reviewed-by: Rick Chen <rick at andestech.com>