[PATCH 20/21] global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace
Tom Rini
trini at konsulko.com
Sat Oct 29 02:27:13 CEST 2022
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace.
Signed-off-by: Tom Rini <trini at konsulko.com>
---
README | 8 +-
arch/arm/cpu/armv7/ls102xa/clock.c | 4 +-
arch/arm/cpu/armv7/ls102xa/cpu.c | 10 +-
arch/arm/cpu/armv7/ls102xa/fdt.c | 4 +-
arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c | 8 +-
arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c | 20 +-
arch/arm/cpu/armv7/ls102xa/psci.S | 16 +-
arch/arm/cpu/armv7/ls102xa/soc.c | 8 +-
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 48 ++--
arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 10 +-
.../armv8/fsl-layerscape/fsl_lsch2_serdes.c | 14 +-
.../armv8/fsl-layerscape/fsl_lsch2_speed.c | 4 +-
.../armv8/fsl-layerscape/fsl_lsch3_serdes.c | 20 +-
.../armv8/fsl-layerscape/fsl_lsch3_speed.c | 10 +-
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 2 +-
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 4 +-
.../cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 2 +-
arch/arm/cpu/armv8/fsl-layerscape/mp.c | 10 +-
arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 4 +-
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 36 +--
.../include/asm/arch-fsl-layerscape/config.h | 28 +--
.../arm/include/asm/arch-fsl-layerscape/cpu.h | 6 +-
.../asm/arch-fsl-layerscape/fsl_icid.h | 26 +--
.../asm/arch-fsl-layerscape/immap_lsch2.h | 48 ++--
.../asm/arch-fsl-layerscape/immap_lsch3.h | 60 ++---
arch/arm/include/asm/arch-imx8/imx-regs.h | 2 +-
arch/arm/include/asm/arch-imx8m/imx-regs.h | 12 +-
arch/arm/include/asm/arch-ls102xa/config.h | 24 +-
.../asm/arch-ls102xa/ls102xa_stream_id.h | 18 +-
arch/arm/include/asm/arch-mx6/imx-regs.h | 12 +-
arch/arm/include/asm/arch-mx7/imx-regs.h | 12 +-
arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 12 +-
arch/arm/mach-imx/cmd_dek.c | 2 +-
arch/arm/mach-imx/cmd_mfgprot.c | 2 +-
arch/arm/mach-imx/mx7/clock.c | 4 +-
arch/arm/mach-imx/mx7ulp/clock.c | 4 +-
arch/arm/mach-imx/speed.c | 12 +-
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 2 +-
arch/powerpc/cpu/mpc85xx/cpu.c | 12 +-
arch/powerpc/cpu/mpc85xx/cpu_init.c | 14 +-
arch/powerpc/cpu/mpc85xx/fdt.c | 10 +-
.../powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 24 +-
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 10 +-
arch/powerpc/cpu/mpc85xx/liodn.c | 14 +-
arch/powerpc/cpu/mpc85xx/mp.c | 4 +-
arch/powerpc/cpu/mpc85xx/speed.c | 4 +-
arch/powerpc/cpu/mpc85xx/start.S | 2 +-
arch/powerpc/cpu/mpc8xxx/law.c | 2 +-
arch/powerpc/cpu/mpc8xxx/srio.c | 8 +-
arch/powerpc/include/asm/config_mpc85xx.h | 81 ++++---
arch/powerpc/include/asm/fsl_liodn.h | 56 ++---
arch/powerpc/include/asm/immap_83xx.h | 2 +-
arch/powerpc/include/asm/immap_85xx.h | 212 +++++++++---------
board/advantech/imx8mp_rsb3720a1/spl.c | 2 +-
board/advantech/imx8qm_rom7720_a1/spl.c | 4 +-
board/bosch/acc/acc.c | 2 +-
board/compulab/cl-som-imx7/cl-som-imx7.c | 2 +-
board/compulab/cm_fx6/cm_fx6.c | 2 +-
board/congatec/cgtqmx8/cgtqmx8.c | 4 +-
board/freescale/common/arm_sleep.c | 8 +-
board/freescale/common/fsl_chain_of_trust.c | 2 +-
board/freescale/common/fsl_validate.c | 4 +-
board/freescale/common/ls102xa_stream_id.c | 2 +-
board/freescale/common/ns_access.c | 2 +-
board/freescale/common/vid.c | 2 +-
board/freescale/imx8mq_evk/spl.c | 2 +-
board/freescale/ls1012aqds/eth.c | 2 +-
board/freescale/ls1012aqds/ls1012aqds.c | 2 +-
board/freescale/ls1012ardb/eth.c | 2 +-
board/freescale/ls1021aiot/ls1021aiot.c | 6 +-
board/freescale/ls1021aqds/ls1021aqds.c | 8 +-
board/freescale/ls1021atsn/ls1021atsn.c | 4 +-
board/freescale/ls1021atwr/ls1021atwr.c | 6 +-
board/freescale/ls1043aqds/eth.c | 4 +-
board/freescale/ls1043aqds/ls1043aqds.c | 10 +-
board/freescale/ls1043ardb/eth.c | 2 +-
board/freescale/ls1043ardb/ls1043ardb.c | 4 +-
board/freescale/ls1046afrwy/eth.c | 4 +-
board/freescale/ls1046afrwy/ls1046afrwy.c | 2 +-
board/freescale/ls1046aqds/eth.c | 2 +-
board/freescale/ls1046aqds/ls1046aqds.c | 10 +-
board/freescale/ls1046ardb/eth.c | 4 +-
board/freescale/ls1046ardb/ls1046ardb.c | 4 +-
board/freescale/ls1088a/eth_ls1088aqds.c | 14 +-
board/freescale/ls1088a/eth_ls1088ardb.c | 6 +-
board/freescale/ls1088a/ls1088a.c | 2 +-
board/freescale/ls2080aqds/eth.c | 16 +-
board/freescale/ls2080ardb/eth_ls2080rdb.c | 6 +-
board/freescale/ls2080ardb/ls2080ardb.c | 4 +-
board/freescale/lx2160a/eth_lx2160aqds.c | 12 +-
board/freescale/lx2160a/eth_lx2160ardb.c | 6 +-
board/freescale/lx2160a/eth_lx2162aqds.c | 12 +-
board/freescale/lx2160a/lx2160a.c | 4 +-
board/freescale/mx53loco/mx53loco.c | 2 +-
board/freescale/p2041rdb/p2041rdb.c | 2 +-
board/freescale/t208xqds/eth_t208xqds.c | 2 +-
board/google/imx8mq_phanbell/spl.c | 2 +-
board/keymile/kmcent2/kmcent2.c | 2 +-
.../keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c | 4 +-
board/kontron/pitx_imx8m/spl.c | 2 +-
board/kontron/sl-mx6ul/spl.c | 2 +-
board/liebherr/mccmon6/spl.c | 4 +-
board/myir/mys_6ulx/spl.c | 2 +-
board/phytec/pcl063/spl.c | 2 +-
board/purism/librem5/spl.c | 2 +-
board/ronetix/imx8mq-cm/spl.c | 2 +-
board/seeed/npi_imx6ull/spl.c | 2 +-
board/socrates/sdram.c | 2 +-
board/toradex/apalis_imx6/apalis_imx6.c | 2 +-
board/toradex/colibri_imx6/colibri_imx6.c | 2 +-
board/traverse/ten64/ten64.c | 2 +-
board/variscite/dart_6ul/spl.c | 2 +-
board/wandboard/spl.c | 4 +-
cmd/blob.c | 2 +-
drivers/crypto/fsl/jobdesc.c | 6 +-
drivers/crypto/fsl/jr.c | 8 +-
drivers/crypto/fsl/sec.c | 2 +-
drivers/ddr/fsl/arm_ddr_gen3.c | 10 +-
drivers/ddr/fsl/ctrl_regs.c | 2 +-
drivers/ddr/fsl/fsl_ddr_gen4.c | 10 +-
drivers/ddr/fsl/fsl_mmdc.c | 2 +-
drivers/ddr/fsl/main.c | 12 +-
drivers/ddr/fsl/mpc85xx_ddr_gen1.c | 4 +-
drivers/ddr/fsl/mpc85xx_ddr_gen2.c | 2 +-
drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 10 +-
drivers/ddr/fsl/util.c | 26 +--
drivers/misc/fsl_devdis.c | 2 +-
drivers/misc/fsl_portals.c | 8 +-
drivers/mmc/fsl_esdhc.c | 2 +-
drivers/mmc/fsl_esdhc_imx.c | 2 +-
drivers/net/fm/eth.c | 2 +-
drivers/net/fm/fm.c | 2 +-
drivers/net/fm/init.c | 6 +-
drivers/net/fm/ls1043.c | 6 +-
drivers/net/fm/ls1046.c | 6 +-
drivers/net/ldpaa_eth/ls1088a.c | 8 +-
drivers/net/ldpaa_eth/ls2080a.c | 6 +-
drivers/net/ldpaa_eth/lx2160a.c | 8 +-
drivers/net/pfe_eth/pfe_eth.c | 2 +-
drivers/net/pfe_eth/pfe_mdio.c | 2 +-
drivers/pci/pcie_fsl.c | 2 +-
drivers/power/power_fsl.c | 2 +-
drivers/qe/qe.c | 8 +-
include/configs/MPC837XERDB.h | 2 +-
include/configs/P1010RDB.h | 2 +-
include/configs/P2041RDB.h | 2 +-
include/configs/T102xRDB.h | 2 +-
include/configs/T104xRDB.h | 2 +-
include/configs/T208xQDS.h | 2 +-
include/configs/T208xRDB.h | 2 +-
include/configs/T4240RDB.h | 2 +-
include/configs/apalis-imx8.h | 4 +-
include/configs/apalis_imx6.h | 4 +-
include/configs/aristainetos2.h | 4 +-
include/configs/cgtqmx8.h | 4 +-
include/configs/cl-som-imx7.h | 4 +-
include/configs/cm_fx6.h | 4 +-
include/configs/colibri-imx6ull.h | 4 +-
include/configs/colibri-imx8x.h | 4 +-
include/configs/colibri_imx6.h | 4 +-
include/configs/colibri_imx7.h | 6 +-
include/configs/dart_6ul.h | 6 +-
include/configs/dh_imx6.h | 4 +-
include/configs/display5.h | 4 +-
include/configs/el6x_common.h | 4 +-
include/configs/embestmx6boards.h | 6 +-
include/configs/ge_bx50v3.h | 2 +-
include/configs/gw_ventana.h | 2 +-
include/configs/imx6_logic.h | 4 +-
include/configs/imx6q-bosch-acc.h | 6 +-
include/configs/imx7-cm.h | 4 +-
include/configs/imx8mm-cl-iot-gate.h | 4 +-
include/configs/imx8mm_data_modul_edm_sbc.h | 4 +-
include/configs/imx8mm_icore_mx8mm.h | 4 +-
include/configs/imx8mn_bsh_smm_s2pro.h | 2 +-
include/configs/imx8mn_var_som.h | 2 +-
include/configs/imx8mp_dhcom_pdk2.h | 4 +-
include/configs/imx8mp_rsb3720.h | 4 +-
include/configs/imx8mq_cm.h | 4 +-
include/configs/imx8mq_evk.h | 4 +-
include/configs/imx8mq_phanbell.h | 4 +-
include/configs/imx8qm_rom7720.h | 4 +-
include/configs/imx93_evk.h | 2 +-
include/configs/kontron-sl-mx6ul.h | 4 +-
include/configs/kontron_pitx_imx8m.h | 4 +-
include/configs/kontron_sl28.h | 4 +-
include/configs/librem5.h | 4 +-
include/configs/liteboard.h | 2 +-
include/configs/ls1012a_common.h | 4 +-
include/configs/ls1012afrwy.h | 2 +-
include/configs/ls1028a_common.h | 4 +-
include/configs/ls1043a_common.h | 2 +-
include/configs/ls1046a_common.h | 2 +-
include/configs/ls1046afrwy.h | 2 +-
include/configs/ls1046ardb.h | 2 +-
include/configs/ls1088a_common.h | 4 +-
include/configs/ls2080a_common.h | 2 +-
include/configs/lx2160a_common.h | 2 +-
include/configs/m53menlo.h | 2 +-
include/configs/mccmon6.h | 4 +-
include/configs/mx51evk.h | 2 +-
include/configs/mx53cx9020.h | 2 +-
include/configs/mx53loco.h | 4 +-
include/configs/mx6cuboxi.h | 2 +-
include/configs/mx6sabre_common.h | 2 +-
include/configs/mx6sabreauto.h | 2 +-
include/configs/mx6sabresd.h | 2 +-
include/configs/mx6slevk.h | 4 +-
include/configs/mx6sllevk.h | 4 +-
include/configs/mx6sxsabreauto.h | 4 +-
include/configs/mx6sxsabresd.h | 2 +-
include/configs/mx6ul_14x14_evk.h | 6 +-
include/configs/mx6ullevk.h | 4 +-
include/configs/mys_6ulx.h | 4 +-
include/configs/nitrogen6x.h | 4 +-
include/configs/novena.h | 4 +-
include/configs/npi_imx6ull.h | 4 +-
include/configs/p1_p2_rdb_pc.h | 2 +-
include/configs/pcl063.h | 4 +-
include/configs/pcl063_ull.h | 4 +-
include/configs/pico-imx6.h | 2 +-
include/configs/pico-imx6ul.h | 2 +-
include/configs/pico-imx7d.h | 4 +-
include/configs/pico-imx8mq.h | 4 +-
include/configs/smegw01.h | 2 +-
include/configs/somlabs_visionsom_6ull.h | 4 +-
include/configs/tqma6.h | 2 +-
include/configs/udoo.h | 2 +-
include/configs/udoo_neo.h | 2 +-
include/configs/usbarmory.h | 2 +-
include/configs/vf610twr.h | 2 +-
include/configs/vining_2000.h | 2 +-
include/configs/wandboard.h | 4 +-
include/configs/warp7.h | 4 +-
include/configs/xpress.h | 2 +-
include/fm_eth.h | 28 +--
include/fsl_sec.h | 4 +-
237 files changed, 862 insertions(+), 863 deletions(-)
diff --git a/README b/README
index edbcc02444a9..db4cb2fe24b8 100644
--- a/README
+++ b/README
@@ -298,7 +298,7 @@ The following options need to be configured:
Enables a workaround for erratum A004510. If set,
then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and
- CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
+ CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional)
@@ -314,7 +314,7 @@ The following options need to be configured:
See Freescale App Note 4493 for more information about
this erratum.
- CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+ CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
This is the value to write into CCSR offset 0x18600
according to the A004510 workaround.
@@ -330,7 +330,7 @@ The following options need to be configured:
Freescale DDR driver in use. This type of DDR controller is
found in mpc83xx, mpc85xx as well as some ARM core SoCs.
- CONFIG_SYS_FSL_DDR_ADDR
+ CFG_SYS_FSL_DDR_ADDR
Freescale DDR memory-mapped register base.
CONFIG_SYS_FSL_IFC_CLK_DIV
@@ -339,7 +339,7 @@ The following options need to be configured:
CONFIG_SYS_FSL_LBC_CLK_DIV
Defines divider of platform clock(clock input to eLBC controller).
- CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+ CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
Physical address from the view of DDR controllers. It is the
same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
it could be different for ARM SoCs.
diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c
index 86b5b21ef862..4e1fe281201f 100644
--- a/arch/arm/cpu/armv7/ls102xa/clock.c
+++ b/arch/arm/cpu/armv7/ls102xa/clock.c
@@ -15,8 +15,8 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info(struct sys_info *sys_info)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_LS1_CLK_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[6] = {
[0] = 0, /* CC1 PPL / 1 */
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 0b3e3b206411..d530e0655bc2 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -228,7 +228,7 @@ void enable_caches(void)
uint get_svr(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
return in_be32(&gur->svr);
}
@@ -237,7 +237,7 @@ uint get_svr(void)
int print_cpuinfo(void)
{
char buf1[32], buf2[32];
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr, major, minor, ver, i;
svr = in_be32(&gur->svr);
@@ -316,7 +316,7 @@ int arch_cpu_init(void)
void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *rcpm2_base =
(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
- struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
u32 state;
icache_enable();
@@ -355,7 +355,7 @@ int arch_cpu_init(void)
/* Set the address at which the secondary core starts from.*/
void smp_set_core_boot_addr(unsigned long addr, int corenr)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
out_be32(&gur->scratchrw[0], addr);
}
@@ -363,7 +363,7 @@ void smp_set_core_boot_addr(unsigned long addr, int corenr)
/* Release the secondary core from holdoff state and kick it */
void smp_kick_all_cpus(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
out_be32(&gur->brrl, 0x2);
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index e63a905eda18..41521c32cebd 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -92,7 +92,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
int off;
int val;
const char *sysclk_path;
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr;
svr = in_be32(&gur->svr);
@@ -105,7 +105,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
else {
ccsr_sec_t __iomem *sec;
- sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
index caf51e17b359..f74d819ea1ea 100644
--- a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
+++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
@@ -39,7 +39,7 @@ int is_serdes_configured(enum srds_prtcl device)
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = in_be32(&gur->rcwsr[4]);
int i;
@@ -74,7 +74,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u64 serdes_prtcl_map = 0;
u32 cfg;
int lane;
@@ -103,14 +103,14 @@ void fsl_serdes_init(void)
#ifdef CONFIG_SYS_FSL_SRDS_1
if (!(serdes1_prtcl_map & (1ULL << NONE)))
serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
- CONFIG_SYS_FSL_SERDES_ADDR,
+ CFG_SYS_FSL_SERDES_ADDR,
RCWSR4_SRDS1_PRTCL_MASK,
RCWSR4_SRDS1_PRTCL_SHIFT);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
if (!(serdes2_prtcl_map & (1ULL << NONE)))
serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
- CONFIG_SYS_FSL_SERDES_ADDR +
+ CFG_SYS_FSL_SERDES_ADDR +
FSL_SRDS_2 * 0x1000,
RCWSR4_SRDS2_PRTCL_MASK,
RCWSR4_SRDS2_PRTCL_SHIFT);
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
index 28a794520747..b4d113dc1e08 100644
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
@@ -31,7 +31,7 @@ static void __secure ls1_save_ddr_head(void)
{
const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
int i;
out_le32(&scfg->sparecr[2], dest);
@@ -57,8 +57,8 @@ static void __secure ls1_fsm_setup(void)
static void __secure ls1_deepsleep_irq_cfg(void)
{
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
/* Mask interrupts from GIC */
@@ -120,8 +120,8 @@ static void __secure ls1_start_fsm(void)
{
void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
/* Set HRSTCR */
setbits_be32(&scfg->hrstcr, 0x80000000);
@@ -155,9 +155,9 @@ static void __secure ls1_start_fsm(void)
static void __secure ls1_deep_sleep(u32 entry_point)
{
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
- struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
#ifdef QIXIS_BASE
u32 tmp;
void *qixis_base = (void *)QIXIS_BASE;
@@ -213,8 +213,8 @@ static void __secure ls1_deep_sleep(u32 entry_point)
#else
static void __secure ls1_sleep(void)
{
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
#ifdef QIXIS_BASE
u32 tmp;
diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
index 3956178369f3..e7c4fbfb4342 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -129,8 +129,8 @@ psci_cpu_on:
mov r1, r4
@ Get DCFG base address
- movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
- movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+ movw r4, #(CFG_SYS_FSL_GUTS_ADDR & 0xffff)
+ movt r4, #(CFG_SYS_FSL_GUTS_ADDR >> 16)
@ Detect target CPU state
ldr r2, [r4, #DCFG_CCSR_BRR]
@@ -141,8 +141,8 @@ psci_cpu_on:
@ Reset target CPU
@ Get SCFG base address
- movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
- movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
+ movw r0, #(CFG_SYS_FSL_SCFG_ADDR & 0xffff)
+ movt r0, #(CFG_SYS_FSL_SCFG_ADDR >> 16)
@ Enable CORE Soft Reset
movw r5, #0
@@ -216,8 +216,8 @@ psci_affinity_info:
mov r1, r4
@ Get RCPM base address
- movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
- movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
+ movw r4, #(CFG_SYS_FSL_RCPM_ADDR & 0xffff)
+ movt r4, #(CFG_SYS_FSL_RCPM_ADDR >> 16)
mov r0, #PSCI_AFFINITY_LEVEL_ON
@@ -236,8 +236,8 @@ out_affinity_info:
.globl psci_system_reset
psci_system_reset:
@ Get DCFG base address
- movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
- movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+ movw r1, #(CFG_SYS_FSL_GUTS_ADDR & 0xffff)
+ movt r1, #(CFG_SYS_FSL_GUTS_ADDR >> 16)
mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
rev r2, r2
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 728efc46f905..1dafa3c1b458 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -54,7 +54,7 @@ struct smmu_stream_id dev_stream_id[] = {
unsigned int get_soc_major_rev(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr, major;
svr = in_be32(&gur->svr);
@@ -113,7 +113,7 @@ static void erratum_a008850_early(void)
/* part 1 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
/* disables propagation of barrier transactions to DDRC from CCI400 */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
@@ -129,7 +129,7 @@ void erratum_a008850_post(void)
/* part 2 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
u32 tmp;
/* enable propagation of barrier transactions to DDRC from CCI400 */
@@ -161,7 +161,7 @@ void erratum_a010315(void)
int arch_soc_init(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 487c0ed5539e..c11341a1d380 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -96,11 +96,11 @@ static struct mm_region early_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
- { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ { CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
#ifdef CONFIG_FSL_IFC
@@ -159,7 +159,7 @@ static struct mm_region early_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
@@ -168,7 +168,7 @@ static struct mm_region early_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+ { CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
CONFIG_SYS_FSL_QSPI_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
@@ -204,7 +204,7 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
@@ -213,12 +213,12 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
- { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ { CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
+ { CFG_SYS_FSL_QSPI_BASE2, CFG_SYS_FSL_QSPI_BASE2,
CONFIG_SYS_FSL_QSPI_SIZE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
@@ -333,7 +333,7 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
@@ -342,7 +342,7 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+ { CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
CONFIG_SYS_FSL_QSPI_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
@@ -401,7 +401,7 @@ struct mm_region *mem_map = early_map;
void cpu_name(char *name)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int i, svr, ver;
svr = gur_in32(&gur->svr);
@@ -430,7 +430,7 @@ void cpu_name(char *name)
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* To start MMU before DDR is available, we create MMU table in SRAM.
- * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
+ * The base address of SRAM is CFG_SYS_FSL_OCRAM_BASE. We use three
* levels of translation tables here to cover 40-bit address space.
* We use 4KB granule size, with 40 bits physical address, T0SZ=24
* Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
@@ -443,7 +443,7 @@ static inline void early_mmu_setup(void)
/* global data is already setup, no allocation yet */
if (el == 3)
- gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
+ gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE;
else
gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
gd->arch.tlb_fillptr = gd->arch.tlb_addr;
@@ -466,7 +466,7 @@ static void fix_pcie_mmu_map(void)
#ifdef CONFIG_ARCH_LS2080A
unsigned int i;
u32 svr, ver;
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
svr = gur_in32(&gur->svr);
ver = SVR_SOC_VER(svr);
@@ -775,7 +775,7 @@ enum boot_src get_boot_src(void)
#if defined(CONFIG_FSL_LSCH3)
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
#elif defined(CONFIG_FSL_LSCH2)
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
#endif
if (current_el() == 2) {
@@ -863,7 +863,7 @@ enum env_location arch_env_get_location(enum env_operation op, int prio)
u32 initiator_type(u32 cluster, int init_id)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
u32 type = 0;
@@ -876,7 +876,7 @@ u32 initiator_type(u32 cluster, int init_id)
u32 cpu_pos_mask(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
int i = 0;
u32 cluster, type, mask = 0;
@@ -897,7 +897,7 @@ u32 cpu_pos_mask(void)
u32 cpu_mask(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
int i = 0, count = 0;
u32 cluster, type, mask = 0;
@@ -930,7 +930,7 @@ int cpu_numcores(void)
int fsl_qoriq_core_to_cluster(unsigned int core)
{
struct ccsr_gur __iomem *gur =
- (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ (void __iomem *)(CFG_SYS_FSL_GUTS_ADDR);
int i = 0, count = 0;
u32 cluster;
@@ -954,7 +954,7 @@ int fsl_qoriq_core_to_cluster(unsigned int core)
u32 fsl_qoriq_core_to_type(unsigned int core)
{
struct ccsr_gur __iomem *gur =
- (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ (void __iomem *)(CFG_SYS_FSL_GUTS_ADDR);
int i = 0, count = 0;
u32 cluster, type;
@@ -979,7 +979,7 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
#ifndef CONFIG_FSL_LSCH3
uint get_svr(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
return gur_in32(&gur->svr);
}
@@ -988,7 +988,7 @@ uint get_svr(void)
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct sys_info sysinfo;
char buf[32];
unsigned int i, core;
@@ -1179,9 +1179,9 @@ int arch_early_init_r(void)
int timer_init(void)
{
- u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+ u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR;
#ifdef CONFIG_FSL_LSCH3
- u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
+ u32 __iomem *cltbenr = (u32 *)CFG_SYS_FSL_PMU_CLTBENR;
#endif
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
defined(CONFIG_ARCH_LS1028A)
@@ -1230,7 +1230,7 @@ int timer_init(void)
}
#if !CONFIG_IS_ENABLED(SYSRESET)
-__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
+__efi_runtime_data u32 __iomem *rstcr = (u32 *)CFG_SYS_FSL_RST_ADDR;
void __efi_runtime reset_cpu(void)
{
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 427de1cb339d..ee734577fca7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -171,9 +171,9 @@ static void fdt_fixup_gic(void *blob)
{
int offset, err;
u64 reg[8];
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int val;
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
int align_64k = 0;
val = gur_in32(&gur->svr);
@@ -355,7 +355,7 @@ static int _fdt_fixup_pci_msi(void *blob, const char *name, int rev)
static void fdt_fixup_msi(void *blob)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int rev;
rev = gur_in32(&gur->svr);
@@ -620,7 +620,7 @@ void fdt_fixup_pfe_firmware(void *blob)
void ft_cpu_setup(void *blob, struct bd_info *bd)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr = gur_in32(&gur->svr);
/* delete crypto node if not on an E-processor */
@@ -635,7 +635,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
fdt_fixup_kaslr(blob);
#endif
- sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
index 60769e139e4e..1541dfb3ec47 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
@@ -40,7 +40,7 @@ int is_serdes_configured(enum srds_prtcl device)
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = gur_in32(&gur->rcwsr[4]);
int i;
@@ -76,7 +76,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
int get_serdes_protocol(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = gur_in32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
@@ -101,7 +101,7 @@ const char *serdes_clock_to_string(u32 clock)
void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg;
int lane;
@@ -142,7 +142,7 @@ __weak int set_serdes_volt(int svdd)
int setup_serdes_volt(u32 svdd)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct ccsr_serdes *serdes1_base;
#ifdef CONFIG_SYS_FSL_SRDS_2
struct ccsr_serdes *serdes2_base;
@@ -168,7 +168,7 @@ int setup_serdes_volt(u32 svdd)
if (svdd_cur == svdd_tar)
return 0;
- serdes1_base = (void *)CONFIG_SYS_FSL_SERDES_ADDR;
+ serdes1_base = (void *)CFG_SYS_FSL_SERDES_ADDR;
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes2_base = (void *)serdes1_base + 0x10000;
#endif
@@ -406,14 +406,14 @@ void fsl_serdes_init(void)
{
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,
- CONFIG_SYS_FSL_SERDES_ADDR,
+ CFG_SYS_FSL_SERDES_ADDR,
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK,
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes_init(FSL_SRDS_2,
- CONFIG_SYS_FSL_SERDES_ADDR,
+ CFG_SYS_FSL_SERDES_ADDR,
FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK,
FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT,
serdes2_prtcl_map);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 898ed09b310a..6440ce714fd1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info(struct sys_info *sys_info)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
/* rcw_tmp is needed to get FMAN clock, or to get cluster group A
* mux 2 clock for LS1043A/LS1046A.
*/
@@ -29,7 +29,7 @@ void get_sys_info(struct sys_info *sys_info)
defined(CONFIG_ARCH_LS1043A)
u32 rcw_tmp;
#endif
- struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
+ struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_CLK_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[8] = {
[0] = 0, /* CC1 PPL / 1 */
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index 181bd9c1b4e5..c0efc341afc1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -86,7 +86,7 @@ int is_serdes_configured(enum srds_prtcl device)
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = 0;
int i;
@@ -134,7 +134,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg;
int lane;
@@ -399,18 +399,18 @@ static void do_pll_lock(u32 cfg,
int setup_serdes_volt(u32 svdd)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct ccsr_serdes __iomem *serdes1_base =
- (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
+ (void *)CFG_SYS_FSL_LSCH3_SERDES_ADDR;
u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
#ifdef CONFIG_SYS_FSL_SRDS_2
struct ccsr_serdes __iomem *serdes2_base =
- (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
+ (void *)(CFG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
#endif
#ifdef CONFIG_SYS_NXP_SRDS_3
struct ccsr_serdes __iomem *serdes3_base =
- (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
+ (void *)(CFG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
#endif
u32 cfg_tmp;
@@ -585,7 +585,7 @@ void fsl_serdes_init(void)
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,
- CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
+ CFG_SYS_FSL_LSCH3_SERDES_ADDR,
FSL_CHASSIS3_SRDS1_REGSR,
FSL_CHASSIS3_SRDS1_PRTCL_MASK,
FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
@@ -593,7 +593,7 @@ void fsl_serdes_init(void)
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes_init(FSL_SRDS_2,
- CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
+ CFG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
FSL_CHASSIS3_SRDS2_REGSR,
FSL_CHASSIS3_SRDS2_PRTCL_MASK,
FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
@@ -601,7 +601,7 @@ void fsl_serdes_init(void)
#endif
#ifdef CONFIG_SYS_NXP_SRDS_3
serdes_init(NXP_SRDS_3,
- CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
+ CFG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
FSL_CHASSIS3_SRDS3_REGSR,
FSL_CHASSIS3_SRDS3_PRTCL_MASK,
FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
@@ -611,7 +611,7 @@ void fsl_serdes_init(void)
int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
char scfg[16], snum[16];
int cfgr = 0;
u32 cfg;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index 58080d0047dd..137778dc136b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -23,13 +23,13 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info(struct sys_info *sys_info)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
- (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR),
- (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR)
+ (void *)(CFG_SYS_FSL_CH3_CLK_GRPA_ADDR),
+ (void *)(CFG_SYS_FSL_CH3_CLK_GRPB_ADDR)
};
struct ccsr_clk_ctrl __iomem *clk_ctrl =
- (void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR);
+ (void *)(CFG_SYS_FSL_CH3_CLK_CTRL_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[16] = {
[0] = 0, /* CC1 PPL / 1 */
@@ -68,7 +68,7 @@ void get_sys_info(struct sys_info *sys_info)
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = get_board_sys_clk();
- int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
+ int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS;
u32 c_pll_sel, cplx_pll;
void *offset;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
index 2d87281ec214..e972603f24f8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
@@ -27,7 +27,7 @@ static void set_icid(struct icid_id_table *tbl, int size)
void set_fman_icids(struct fman_icid_id_table *tbl, int size)
{
int i;
- ccsr_fman_t *fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
+ ccsr_fman_t *fm = (void *)CFG_SYS_FSL_FM1_ADDR;
for (i = 0; i < size; i++) {
out_be32(&fm->fm_bmi_common.fmbm_ppid[tbl[i].port_id - 1],
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 87410c73a920..4358c6ed11c0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -325,8 +325,8 @@ ENDPROC(fsl_ocram_init)
ENTRY(fsl_clear_ocram)
/* Clear OCRAM */
- ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
- ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
+ ldr x0, =CFG_SYS_FSL_OCRAM_BASE
+ ldr x1, =(CFG_SYS_FSL_OCRAM_BASE + CFG_SYS_FSL_OCRAM_SIZE)
mov x2, #0
clear_loop:
str x2, [x0]
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
index 26f8a4982692..fe667f06c395 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
@@ -53,7 +53,7 @@ static struct serdes_config *serdes_cfg_tbl[] = {
bool soc_has_mac1(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr = gur_in32(&gur->svr);
unsigned int version = SVR_SOC_VER(svr);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index 722211914936..ce0c46ad0d4e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -48,8 +48,8 @@ void update_os_arch_secondary_cores(uint8_t os_arch)
#ifdef CONFIG_FSL_LSCH3
static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_reset __iomem *rst = (void *)(CFG_SYS_FSL_RST_ADDR);
u32 mpidr = 0;
mpidr = ((cluster << 8) | core);
@@ -73,13 +73,13 @@ static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
int fsl_layerscape_wake_seconday_cores(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
#ifdef CONFIG_FSL_LSCH3
- struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+ struct ccsr_reset __iomem *rst = (void *)(CFG_SYS_FSL_RST_ADDR);
u32 svr, ver, cluster, type;
int j = 0, cluster_cores = 0;
#elif defined(CONFIG_FSL_LSCH2)
- struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
+ struct ccsr_scfg __iomem *scfg = (void *)(CFG_SYS_FSL_SCFG_ADDR);
#endif
u32 cores, cpu_up_mask = 1;
int i, timeout = 10;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
index b9894d41bbdd..117b7a053c51 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
@@ -253,7 +253,7 @@ int ppa_init(void)
#endif
#ifdef CONFIG_FSL_LSCH3
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
boot_loc_ptr_l = &gur->bootlocptrl;
boot_loc_ptr_h = &gur->bootlocptrh;
@@ -261,7 +261,7 @@ int ppa_init(void)
loadable_l = &gur->scratchrw[4];
loadable_h = &gur->scratchrw[5];
#elif defined(CONFIG_FSL_LSCH2)
- struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
+ struct ccsr_scfg __iomem *scfg = (void *)(CFG_SYS_FSL_SCFG_ADDR);
boot_loc_ptr_l = &scfg->scratchrw[1];
boot_loc_ptr_h = &scfg->scratchrw[0];
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 515dbe02fd79..89a6262c1282 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -80,7 +80,7 @@ int ls_gic_rd_tables_init(void *blob)
bool soc_has_dp_ddr(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr);
/* LS2085A, LS2088A, LS2048A has DP_DDR */
@@ -94,7 +94,7 @@ bool soc_has_dp_ddr(void)
bool soc_has_aiop(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr);
/* LS2085A has AIOP */
@@ -249,13 +249,13 @@ static void erratum_a008336(void)
#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
u32 *eddrtqcr1;
-#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
- eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
+#ifdef CFG_SYS_FSL_DCSR_DDR_ADDR
+ eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
if (fsl_ddr_get_version(0) == 0x50200)
out_le32(eddrtqcr1, 0x63b30002);
#endif
-#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
- eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
+#ifdef CFG_SYS_FSL_DCSR_DDR2_ADDR
+ eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
if (fsl_ddr_get_version(0) == 0x50200)
out_le32(eddrtqcr1, 0x63b30002);
#endif
@@ -271,8 +271,8 @@ static void erratum_a008514(void)
#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
u32 *eddrtqcr1;
-#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
- eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
+#ifdef CFG_SYS_FSL_DCSR_DDR3_ADDR
+ eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
out_le32(eddrtqcr1, 0x63b20002);
#endif
#endif
@@ -412,7 +412,7 @@ void fsl_lsch3_early_init_f(void)
/* Get VDD in the unit mV from voltage ID */
int get_core_volt_from_fuse(void)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
int vdd;
u32 fusesr;
u8 vid;
@@ -462,7 +462,7 @@ int get_core_volt_from_fuse(void)
static void erratum_a009660(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
- u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
+ u32 *eddrtqcr1 = (void *)CFG_SYS_FSL_SCFG_ADDR + 0x20c;
out_be32(eddrtqcr1, 0x63b20042);
#endif
}
@@ -473,7 +473,7 @@ static void erratum_a008850_early(void)
/* part 1 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
/* Skip if running at lower exception level */
if (current_el() < 3)
@@ -493,7 +493,7 @@ void erratum_a008850_post(void)
/* part 2 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
u32 tmp;
/* Skip if running at lower exception level */
@@ -526,21 +526,21 @@ void erratum_a010315(void)
static void erratum_a010539(void)
{
#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 porsr1;
porsr1 = in_be32(&gur->porsr1);
porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
porsr1);
- out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
+ out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
#endif
}
/* Get VDD in the unit mV from voltage ID */
int get_core_volt_from_fuse(void)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
int vdd;
u32 fusesr;
u8 vid;
@@ -588,7 +588,7 @@ static int setup_core_volt(u32 vdd)
#ifdef CONFIG_SYS_FSL_DDR
static void ddr_enable_0v9_volt(bool en)
{
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
u32 tmp;
tmp = ddr_in32(&ddr->ddr_cdr1);
@@ -629,7 +629,7 @@ int setup_chip_volt(void)
#ifdef CONFIG_FSL_PFE
void init_pfe_scfg_dcfg_regs(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 ecccr2;
out_be32(&scfg->pfeasbcr,
@@ -653,7 +653,7 @@ void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
enum boot_src src;
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 5824778ca286..ff752c21b14d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -24,7 +24,7 @@
#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
#ifdef CONFIG_ARCH_LS2080A
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define SRDS_MAX_LANES 8
#define CONFIG_SYS_PAGE_SIZE 0x10000
#ifndef L1_CACHE_BYTES
@@ -32,9 +32,9 @@
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
#endif
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
+#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
/* DDR */
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
@@ -95,7 +95,7 @@
#define EPU_EPGCR 0x700060000ULL
#elif defined(CONFIG_ARCH_LS1088A)
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define SRDS_MAX_LANES 4
@@ -126,9 +126,9 @@
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
/* DCFG - GUR */
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
+#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
/* LX2160A/LX2162A Soc Support */
#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
@@ -139,13 +139,13 @@
#define L1_CACHE_SHIFT 6
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
#endif
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
#define CONFIG_SYS_PAGE_SIZE 0x10000
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
+#define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
/* DDR */
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
@@ -161,7 +161,7 @@
/* DCFG - GUR */
#elif defined(CONFIG_ARCH_LS1028A)
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_FSL_TZASC_400
/* TZ Protection Controller Definitions */
@@ -180,9 +180,9 @@
#define SRDS_MAX_LANES 4
#define SRDS_BITS_PER_LANE 4
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */
-#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
+#define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
@@ -200,9 +200,9 @@
/* DCFG - GUR */
#elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
+#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
#define DCSR_DCFG_SBEESR2 0x20140534
#define DCSR_DCFG_MBEESR2 0x20140544
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index c51b65ea36d9..4db479140ea2 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -10,7 +10,7 @@
#ifdef CONFIG_FSL_LSCH3
#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
-#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
+#define CFG_SYS_FSL_QSPI_BASE1 0x20000000
#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
#ifndef CONFIG_NXP_LSCH3_2
#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
@@ -19,7 +19,7 @@
#endif
#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
-#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
+#define CFG_SYS_FSL_QSPI_BASE2 0x400000000
#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
#ifndef CONFIG_NXP_LSCH3_2
#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
@@ -73,7 +73,7 @@
#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
-#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
+#define CFG_SYS_FSL_QSPI_BASE 0x40000000
#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
#define CONFIG_SYS_FSL_IFC_BASE 0x60000000
#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index 8af0d35d27b7..9cddb41a89c8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -70,7 +70,7 @@ void fdt_fixup_icid(void *blob);
#define SET_SCFG_ICID(compat, streamid, name, compataddr) \
SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
- offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
+ offsetof(struct ccsr_scfg, name) + CFG_SYS_FSL_SCFG_ADDR, \
compataddr, SCFG_IS_LE)
#define SET_USB_ICID(usb_num, compat, streamid) \
@@ -83,7 +83,7 @@ void fdt_fixup_icid(void *blob);
#define SET_SDHC_ICID(streamid) \
SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\
- CONFIG_SYS_FSL_ESDHC_ADDR)
+ CFG_SYS_FSL_ESDHC_ADDR)
#define SET_EDMA_ICID(streamid) \
SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\
@@ -102,14 +102,14 @@ void fdt_fixup_icid(void *blob);
#define SET_QMAN_ICID(streamid) \
SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
offsetof(struct ccsr_qman, liodnr) + \
- CONFIG_SYS_FSL_QMAN_ADDR, \
- CONFIG_SYS_FSL_QMAN_ADDR, false)
+ CFG_SYS_FSL_QMAN_ADDR, \
+ CFG_SYS_FSL_QMAN_ADDR, false)
#define SET_BMAN_ICID(streamid) \
SET_ICID_ENTRY("fsl,bman", streamid, streamid, \
offsetof(struct ccsr_bman, liodnr) + \
- CONFIG_SYS_FSL_BMAN_ADDR, \
- CONFIG_SYS_FSL_BMAN_ADDR, false)
+ CFG_SYS_FSL_BMAN_ADDR, \
+ CFG_SYS_FSL_BMAN_ADDR, false)
#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
{ .port_id = (_port_id), .icid = (streamid) }
@@ -119,8 +119,8 @@ void fdt_fixup_icid(void *blob);
#define SET_SEC_QI_ICID(streamid) \
SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
0, offsetof(ccsr_sec_t, qilcr_ls) + \
- CONFIG_SYS_FSL_SEC_ADDR, \
- CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
+ CFG_SYS_FSL_SEC_ADDR, \
+ CFG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
extern struct fman_icid_id_table fman_icid_tbl[];
extern int fman_icid_tbl_sz;
@@ -137,7 +137,7 @@ extern int fman_icid_tbl_sz;
#define SET_GUR_ICID(compat, streamid, name, compataddr) \
SET_ICID_ENTRY(compat, streamid, streamid, \
- offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \
+ offsetof(struct ccsr_gur, name) + CFG_SYS_FSL_GUTS_ADDR, \
compataddr, GUR_IS_LE)
#define SET_USB_ICID(usb_num, compat, streamid) \
@@ -180,24 +180,24 @@ extern int fman_icid_tbl_sz;
SET_ICID_ENTRY( \
(CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \
(FSL_SEC_JR##jr_num##_OFFSET == \
- SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \
+ SEC_JR3_OFFSET + CFG_SYS_FSL_SEC_OFFSET) \
? NULL \
: "fsl,sec-v4.0-job-ring"), \
streamid, \
SEC_ICID_REG_VAL(streamid), \
offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
- CONFIG_SYS_FSL_SEC_ADDR, \
+ CFG_SYS_FSL_SEC_ADDR, \
FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)
#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
- CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
+ CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
- CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
+ CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
extern struct icid_id_table icid_tbl[];
extern int icid_tbl_sz;
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 2b73647ab4a9..e8bd8d27136c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -14,18 +14,18 @@
#define CONFIG_SYS_DCSRBAR 0x20000000
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
-#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
+#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
-#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
-#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
-#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
-#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
-#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
-#define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000)
-#define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000)
-#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
-#define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
+#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
+#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
+#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
+#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
+#define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
+#define CFG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000)
+#define CFG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000)
+#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
+#define CFG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
@@ -65,7 +65,7 @@
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680
-#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
+#define CFG_SYS_FSL_TIMER_ADDR 0x02b00000
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
@@ -165,24 +165,24 @@ struct sys_info {
unsigned long freq_qman;
};
-#define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000
+#define CFG_SYS_FSL_FM1_OFFSET 0xa00000
-#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
-#define CONFIG_SYS_FSL_FM1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
-#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
+#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
+#define CFG_SYS_FSL_FM1_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_OFFSET)
+#define CFG_SYS_FSL_FM1_DTSEC1_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_DTSEC1_OFFSET)
-#define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull
-#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET
+#define CFG_SYS_FSL_SEC_OFFSET 0x700000ull
+#define CFG_SYS_FSL_JR0_OFFSET 0x710000ull
+#define FSL_SEC_JR0_OFFSET CFG_SYS_FSL_JR0_OFFSET
#define FSL_SEC_JR1_OFFSET 0x720000ull
#define FSL_SEC_JR2_OFFSET 0x730000ull
#define FSL_SEC_JR3_OFFSET 0x740000ull
-#define CONFIG_SYS_FSL_SEC_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 570397b3c04c..f1ffb2327d63 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -9,19 +9,19 @@
#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
#define __ARCH_FSL_LSCH3_IMMAP_H_
-#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
-#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
-#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
-#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
+#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
+#define CFG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
+#define CFG_SYS_FSL_DDR3_ADDR 0x08210000
+#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
+#define CFG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
-#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
+#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
#else
-#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
+#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
#endif
-#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
-#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
-#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
+#define CFG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
+#define CFG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
+#define CFG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
#ifndef CONFIG_NXP_LSCH3_2
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
#else
@@ -29,8 +29,8 @@
#define SYS_NXP_FSPI_LUTKEY_BASE_ADDR 0x18
#define SYS_NXP_FSPI_LUT_BASE_ADDR 0x200
#endif
-#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
-#define FSL_ESDHC1_BASE_ADDR CONFIG_SYS_FSL_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
+#define FSL_ESDHC1_BASE_ADDR CFG_SYS_FSL_ESDHC_ADDR
#define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000)
#ifndef CONFIG_NXP_LSCH3_2
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
@@ -38,20 +38,20 @@
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
#define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000
-#define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000
-#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
+#define CFG_SYS_FSL_TIMER_ADDR 0x023e0000
+#define CFG_SYS_FSL_PMU_CLTBENR (CFG_SYS_FSL_PMU_ADDR + \
0x18A0)
-#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
-#define FSL_LSCH3_SVR (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4)
+#define FSL_PMU_PCTBENR_OFFSET (CFG_SYS_FSL_PMU_ADDR + 0x8A0)
+#define FSL_LSCH3_SVR (CFG_SYS_FSL_GUTS_ADDR + 0xA4)
-#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
-#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
-#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
-#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
+#define CFG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
+#define CFG_SYS_FSL_WRIOP1_MDIO1 (CFG_SYS_FSL_WRIOP1_ADDR + 0x16000)
+#define CFG_SYS_FSL_WRIOP1_MDIO2 (CFG_SYS_FSL_WRIOP1_ADDR + 0x17000)
+#define CFG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
-#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
+#define CFG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
+#define CFG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
+#define CFG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
@@ -108,16 +108,16 @@
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
/* SEC */
-#define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull
-#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET
+#define CFG_SYS_FSL_SEC_OFFSET 0x07000000ull
+#define CFG_SYS_FSL_JR0_OFFSET 0x07010000ull
+#define FSL_SEC_JR0_OFFSET CFG_SYS_FSL_JR0_OFFSET
#define FSL_SEC_JR1_OFFSET 0x07020000ull
#define FSL_SEC_JR2_OFFSET 0x07030000ull
#define FSL_SEC_JR3_OFFSET 0x07040000ull
-#define CONFIG_SYS_FSL_SEC_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h
index 3d32b7a02a18..f5691620c48e 100644
--- a/arch/arm/include/asm/arch-imx8/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8/imx-regs.h
@@ -47,6 +47,6 @@
#define USB_BASE_ADDR 0x5b0d0000
#define USB_PHY0_BASE_ADDR 0x5b100000
-#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
+#define CFG_SYS_FSL_SEC_ADDR (0x31400000)
#endif /* __ASM_ARCH_IMX8_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 29d5baaab8b8..586847f32e25 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -87,12 +87,12 @@
#define CAAM_ARB_BASE_ADDR (0x00100000)
#define CAAM_ARB_END_ADDR (0x00107FFF)
#define CAAM_IPS_BASE_ADDR (0x30900000)
-#define CONFIG_SYS_FSL_SEC_OFFSET (0)
-#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
- CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000)
-#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
- CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_OFFSET (0)
+#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
+ CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_OFFSET (0x1000)
+#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
+ CFG_SYS_FSL_JR0_OFFSET)
#if !defined(__ASSEMBLY__)
#include <asm/types.h>
#include <linux/bitops.h>
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 0e32828b4f1e..e85918eb7ec5 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -17,25 +17,25 @@
#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)
#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
-#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
+#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
+#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
-#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
-#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
-#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
-#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
+#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
+#define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
+#define CFG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
+#define CFG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
-#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
-#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
-#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
-#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
+#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
+#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
+#define CFG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
+#define CFG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000
+#define CFG_SYS_FSL_SEC_OFFSET 0x00700000
+#define CFG_SYS_FSL_JR0_OFFSET 0x00710000
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
index 93b0a26091e7..fb5ded890783 100644
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
@@ -29,30 +29,30 @@
#define SET_SEC_JR_LIODN_ENTRY(jrnum, liodnA, liodnB) \
SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB, \
offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \
SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
/* This is a bit evil since we treat rtic param as both a string & hex value */
#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
liodnA, \
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
liodnA, \
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, 0)
+ CFG_SYS_FSL_SEC_OFFSET, 0)
struct liodn_id_table {
const char *compat;
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 56b3a58d478a..72944af18a40 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -238,12 +238,12 @@
#endif
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
-#define CONFIG_SYS_FSL_SEC_OFFSET 0
-#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \
- CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
-#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
- CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_OFFSET 0
+#define CFG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \
+ CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_OFFSET 0x1000
+#define CFG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
+ CFG_SYS_FSL_JR0_OFFSET)
#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index 1e9d11b7a5c1..c863cd9da360 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -215,12 +215,12 @@
#define FEC_QUIRK_ENET_MAC
#define SNVS_LPGPR 0x68
-#define CONFIG_SYS_FSL_SEC_OFFSET 0
-#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
- CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
-#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
- CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_OFFSET 0
+#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
+ CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_OFFSET 0x1000
+#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
+ CFG_SYS_FSL_JR0_OFFSET)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/mach-imx/regs-lcdif.h>
#include <asm/types.h>
diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
index ffa170f4d255..33a699ff71a9 100644
--- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
@@ -228,12 +228,12 @@
#define CAAM_IPS_BASE_ADDR (AIPS2_BASE + 0x240000) /* 40240000 */
-#define CONFIG_SYS_FSL_SEC_OFFSET 0
-#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
- CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
-#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
- CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_OFFSET 0
+#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
+ CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_OFFSET 0x1000
+#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
+ CFG_SYS_FSL_JR0_OFFSET)
#define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32)))
#define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33)))
diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c
index 04c4b20a84bc..b65bf874b837 100644
--- a/arch/arm/mach-imx/cmd_dek.c
+++ b/arch/arm/mach-imx/cmd_dek.c
@@ -40,7 +40,7 @@ static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
hab_caam_clock_enable(1);
- u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR +
+ u32 out_jr_size = sec_in32(CFG_SYS_FSL_JR0_ADDR +
FSL_CAAM_ORSR_JRa_OFFSET);
if (out_jr_size != FSL_CAAM_MAX_JR_SIZE)
sec_init();
diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c
index ec8a8756f7fc..9576b48dde30 100644
--- a/arch/arm/mach-imx/cmd_mfgprot.c
+++ b/arch/arm/mach-imx/cmd_mfgprot.c
@@ -41,7 +41,7 @@ static int do_mfgprot(struct cmd_tbl *cmdtp, int flag, int argc, char *const arg
/* Enable HAB clock */
hab_caam_clock_enable(1);
- u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR +
+ u32 out_jr_size = sec_in32(CFG_SYS_FSL_JR0_ADDR +
FSL_CAAM_ORSR_JRa_OFFSET);
if (out_jr_size != FSL_CAAM_MAX_JR_SIZE)
diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c
index 304a0303134a..88f6fe027482 100644
--- a/arch/arm/mach-imx/mx7/clock.c
+++ b/arch/arm/mach-imx/mx7/clock.c
@@ -30,9 +30,9 @@ DECLARE_GLOBAL_DATA_PTR;
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC_IMX
-#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
+#if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
#else
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c
index 6191153917f7..37d8565c20fc 100644
--- a/arch/arm/mach-imx/mx7ulp/clock.c
+++ b/arch/arm/mach-imx/mx7ulp/clock.c
@@ -18,9 +18,9 @@ DECLARE_GLOBAL_DATA_PTR;
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC_IMX
-#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
+#if CFG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
+#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#endif
#endif
diff --git a/arch/arm/mach-imx/speed.c b/arch/arm/mach-imx/speed.c
index b729187ec817..0e81cc880a1a 100644
--- a/arch/arm/mach-imx/speed.c
+++ b/arch/arm/mach-imx/speed.c
@@ -21,21 +21,21 @@ int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC_IMX
#ifdef CONFIG_FSL_USDHC
-#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
+#if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
#else
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
#endif
#else
-#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
+#if CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
#else
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index ff73596ba903..ed890114ec48 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -84,7 +84,7 @@ static void check_erratum_a4849(uint32_t svr)
static void check_erratum_a4580(uint32_t svr)
{
const serdes_corenet_t __iomem *srds_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
unsigned int lane;
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 432d4b11dcf3..49a1aac42b53 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -98,7 +98,7 @@ int checkcpu (void)
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
if (SVR_SOC_VER(svr) == SVR_T4080) {
ccsr_rcpm_t *rcpm =
- (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+ (void __iomem *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
FSL_CORENET_DEVDISR2_DTSEC1_9);
@@ -540,16 +540,16 @@ static void dump_spd_ddr_reg(void)
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
switch (i) {
case 0:
- ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr[i] = (void *)CFG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
- ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr[i] = (void *)CFG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
- ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr[i] = (void *)CFG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 46b44c51961c..2367b0932b7e 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -160,7 +160,7 @@ void disable_cpc_sram(void)
{
int i;
- cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+ cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
@@ -217,7 +217,7 @@ void enable_cpc(void)
char cpc_subarg[16];
bool have_hwconfig = false;
int cpc_args = 0;
- cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+ cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
/* Extract hwconfig from environment */
ret = env_get_f("hwconfig", buffer, sizeof(buffer));
@@ -271,7 +271,7 @@ void enable_cpc(void)
static void invalidate_cpc(void)
{
int i;
- cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+ cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
/* skip CPC when it used as all SRAM */
@@ -300,7 +300,7 @@ static void invalidate_cpc(void)
static void corenet_tb_init(void)
{
volatile ccsr_rcpm_t *rcpm =
- (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+ (void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
volatile ccsr_pic_t *pic =
(void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
u32 whoami = in_be32(&pic->whoami);
@@ -476,7 +476,7 @@ int enable_cluster_l2(void)
do {
int j, cluster_valid = 0;
- l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
+ l2cache = (void __iomem *)(CFG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
cluster = in_be32(&gur->tp_cluster[i].lower);
@@ -518,7 +518,7 @@ int l2cache_init(void)
#ifdef CONFIG_L2_CACHE
ccsr_l2cache_t *l2cache = (void __iomem *)CFG_SYS_MPC85xx_L2_ADDR;
#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
- struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
+ struct ccsr_cluster_l2 * l2cache = (void __iomem *)CFG_SYS_FSL_CLUSTER_1_L2;
#endif
puts ("L2: ");
@@ -664,7 +664,7 @@ int cpu_init_r(void)
const char *spin;
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
- ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t __iomem *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 266a61163f50..9d7e7d2e81eb 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -164,7 +164,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
static inline void ft_fixup_l3cache(void *blob, int off)
{
u32 line_size, num_ways, size, num_sets;
- cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
+ cpc_corenet_t *cpc = (void *)CFG_SYS_FSL_CPC_ADDR;
u32 cfg0 = in_be32(&cpc->cpccfg0);
size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
@@ -299,7 +299,7 @@ static inline void ft_fixup_l2cache(void *blob)
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
#else
struct ccsr_cluster_l2 *l2cache =
- (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
+ (struct ccsr_cluster_l2 __iomem *)(CFG_SYS_FSL_CLUSTER_1_L2);
u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
#endif
u32 size, line_size, num_ways, num_sets;
@@ -466,11 +466,11 @@ static void ft_fixup_dpaa_clks(void *blob)
get_sys_info(&sysinfo);
#ifdef CONFIG_SYS_DPAA_FMAN
- ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
+ ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM1_OFFSET,
sysinfo.freq_fman[0]);
#if (CONFIG_SYS_NUM_FMAN == 2)
- ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
+ ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM2_OFFSET,
sysinfo.freq_fman[1]);
#endif
#endif
@@ -611,7 +611,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
else {
ccsr_sec_t __iomem *sec;
- sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 1a30395256b9..3a6ce32f7e6c 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -21,10 +21,10 @@ static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
#ifdef CONFIG_SYS_FSL_SRDS_2
static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_3
+#ifdef CFG_SYS_FSL_SRDS_3
static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_4
+#ifdef CFG_SYS_FSL_SRDS_4
static u8 serdes4_prtcl_map[SERDES_PRCTL_COUNT];
#endif
@@ -104,13 +104,13 @@ int is_serdes_configured(enum srds_prtcl device)
ret |= serdes2_prtcl_map[device];
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_3
+#ifdef CFG_SYS_FSL_SRDS_3
if (!serdes3_prtcl_map[NONE])
fsl_serdes_init();
ret |= serdes3_prtcl_map[device];
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_4
+#ifdef CFG_SYS_FSL_SRDS_4
if (!serdes4_prtcl_map[NONE])
fsl_serdes_init();
@@ -139,13 +139,13 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
break;
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_3
+#ifdef CFG_SYS_FSL_SRDS_3
case FSL_SRDS_3:
cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
break;
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_4
+#ifdef CFG_SYS_FSL_SRDS_4
case FSL_SRDS_4:
cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
@@ -351,28 +351,28 @@ void fsl_serdes_init(void)
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
+ CFG_SYS_FSL_CORENET_SERDES_ADDR,
FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes_init(FSL_SRDS_2,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
+ CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT,
serdes2_prtcl_map);
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_3
+#ifdef CFG_SYS_FSL_SRDS_3
serdes_init(FSL_SRDS_3,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
+ CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT,
serdes3_prtcl_map);
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_4
+#ifdef CFG_SYS_FSL_SRDS_4
serdes_init(FSL_SRDS_4,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
+ CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT,
serdes4_prtcl_map);
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 1d35733c013d..437ecde61559 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -109,7 +109,7 @@ int serdes_get_bank_by_lane(int lane)
int serdes_lane_enabled(int lane)
{
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
int bank = lanes[lane].bank;
int word = lanes[lane].lpd / 32;
@@ -257,7 +257,7 @@ void serdes_reset_rx(enum srds_prtcl device)
if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
return;
- regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ regs = (typeof(regs))CFG_SYS_FSL_CORENET_SERDES_ADDR;
prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
__serdes_reset_rx(regs, prtcl, device);
@@ -466,7 +466,7 @@ static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg)
static void wait_for_rstdone(unsigned int bank)
{
serdes_corenet_t *srds_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
unsigned long long end_tick;
u32 rstctl;
@@ -527,7 +527,7 @@ void fsl_serdes_init(void)
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
return;
- srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
+ srds_regs = (void *)(CFG_SYS_FSL_CORENET_SERDES_ADDR);
cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
debug("Using SERDES configuration 0x%x, lane settings:\n", cfg);
@@ -601,7 +601,7 @@ void fsl_serdes_init(void)
serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2;
break;
default:
- srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
+ srds2_regs = (void *)CFG_SYS_FSL_CORENET_SERDES2_ADDR;
/* We don't need bank 4, so power it down */
setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD);
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index a08400249492..3aa3ca4c3ee0 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -76,7 +76,7 @@ static void set_fman_liodn(struct fman_liodn_id_table *tbl, int size)
static void setup_sec_liodn_base(void)
{
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
u32 base;
if (!IS_E_PROCESSOR(get_svr()))
@@ -101,12 +101,12 @@ static void setup_fman_liodn_base(enum fsl_dpaa_dev dev,
switch(dev) {
case FSL_HW_PORTAL_FMAN1:
- fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
+ fm = (void *)CFG_SYS_FSL_FM1_ADDR;
break;
#if (CONFIG_SYS_NUM_FMAN == 2)
case FSL_HW_PORTAL_FMAN2:
- fm = (void *)CONFIG_SYS_FSL_FM2_ADDR;
+ fm = (void *)CFG_SYS_FSL_FM2_ADDR;
break;
#endif
default:
@@ -130,7 +130,7 @@ static void setup_fman_liodn_base(enum fsl_dpaa_dev dev,
static void setup_pme_liodn_base(void)
{
#ifdef CONFIG_SYS_DPAA_PME
- ccsr_pme_t *pme = (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
+ ccsr_pme_t *pme = (void *)CFG_SYS_FSL_CORENET_PME_ADDR;
u32 base = (liodn_bases[FSL_HW_PORTAL_PME].id[0] << 16) |
liodn_bases[FSL_HW_PORTAL_PME].id[1];
@@ -141,7 +141,7 @@ static void setup_pme_liodn_base(void)
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
static void setup_raide_liodn_base(void)
{
- struct ccsr_raide *raide = (void *)CONFIG_SYS_FSL_RAID_ENGINE_ADDR;
+ struct ccsr_raide *raide = (void *)CFG_SYS_FSL_RAID_ENGINE_ADDR;
/* setup raid engine liodn base for data/desc ; both set to 47 */
u32 base = (liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0] << 16) |
@@ -155,7 +155,7 @@ static void setup_raide_liodn_base(void)
static void set_rman_liodn(struct liodn_id_table *tbl, int size)
{
int i;
- struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR;
+ struct ccsr_rman *rman = (void *)CFG_SYS_FSL_CORENET_RMAN_ADDR;
for (i = 0; i < size; i++) {
/* write the RMan block number */
@@ -168,7 +168,7 @@ static void set_rman_liodn(struct liodn_id_table *tbl, int size)
static void setup_rman_liodn_base(struct liodn_id_table *tbl, int size)
{
int i;
- struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR;
+ struct ccsr_rman *rman = (void *)CFG_SYS_FSL_CORENET_RMAN_ADDR;
u32 base = liodn_bases[FSL_HW_PORTAL_RMAN].id[0];
out_be32(&rman->mmliodnbr, base);
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index e1469eb296a0..f109ecb9ff76 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -265,8 +265,8 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
struct law_entry e;
gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
- rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+ ccm = (void *)(CFG_SYS_FSL_CORENET_CCM_ADDR);
+ rcpm = (void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
whoami = in_be32(&pic->whoami);
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index a7004a670bbc..31d048192767 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -26,14 +26,14 @@ void get_sys_info(sys_info_t *sys_info)
{
volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_CORENET
- volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
+ volatile ccsr_clk_t *clk = (void *)(CFG_SYS_FSL_CORENET_CLK_ADDR);
unsigned int cpu;
#ifdef CONFIG_HETROGENOUS_CLUSTERS
unsigned int dsp_cpu;
uint rcw_tmp1, rcw_tmp2;
#endif
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
- int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
+ int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS;
#endif
__maybe_unused u32 svr;
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 024414e9ff96..534175697435 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -966,7 +966,7 @@ delete_ccsr_l2_tlb:
erratum_set_dcsr 0xb0e38 0xe0400000
erratum_set_dcsr 0xb0008 0x00900000
erratum_set_dcsr 0xb0e40 0xe00a0000
- erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+ erratum_set_ccsr 0x18600 CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
#ifdef CONFIG_RAMBOOT_PBL
erratum_set_ccsr 0x10f00 0x495e5000
#else
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index 38ceb8a93749..bcbbb7416b9b 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS
#ifdef CONFIG_FSL_CORENET
-#define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR)
+#define LAW_BASE (CFG_SYS_FSL_CORENET_CCM_ADDR)
#define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar)
#define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh)
#define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl)
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 62524a243365..c815d19384bd 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -79,9 +79,9 @@ static int srio_erratum_a004034(u8 port)
int idx, first, last;
u32 i;
unsigned long long end_tick;
- struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+ struct ccsr_rio *srio_regs = (void *)CFG_SYS_FSL_SRIO_ADDR;
- srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
+ srds_regs = (void *)(CFG_SYS_FSL_CORENET_SERDES_ADDR);
conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
>> (12 - port * 4)) & 0x3;
init_lane = (in_be32((void *)&srio_regs->lp_serial
@@ -291,7 +291,7 @@ void srio_init(void)
#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
void srio_boot_master(int port)
{
- struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+ struct ccsr_rio *srio = (void *)CFG_SYS_FSL_SRIO_ADDR;
/* set port accept-all */
out_be32((void *)&srio->impl.port[port - 1].ptaacr,
@@ -343,7 +343,7 @@ void srio_boot_master(int port)
void srio_boot_master_release_slave(int port)
{
- struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+ struct ccsr_rio *srio = (void *)CFG_SYS_FSL_SRIO_ADDR;
u32 escsr;
debug("SRIOBOOT - MASTER: "
"Check the port status and release slave core ...\n");
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index d3d4e9c053f4..25d1b4861746 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -17,10 +17,10 @@
#include <fsl_ddrc_version.h>
#if defined(CONFIG_ARCH_MPC8548)
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 1
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
@@ -59,30 +59,30 @@
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_P2020)
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P3041)
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
#define CONFIG_SYS_NUM_FMAN 2
@@ -91,11 +91,11 @@
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
#elif defined(CONFIG_ARCH_P5040)
#define CONFIG_SYS_NUM_FMAN 2
@@ -104,7 +104,7 @@
#define CONFIG_SYS_NUM_FM2_DTSEC 5
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_FSL_SDHC_V2_3
@@ -118,7 +118,7 @@
#elif defined(CONFIG_ARCH_T4240)
#ifdef CONFIG_ARCH_T4240
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_SYS_NUM_FM2_DTSEC 8
@@ -131,17 +131,17 @@
#endif
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
-#define CONFIG_SYS_FSL_SRDS_3
-#define CONFIG_SYS_FSL_SRDS_4
+#define CFG_SYS_FSL_SRDS_3
+#define CFG_SYS_FSL_SRDS_4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_PME_CLK 0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FM1_CLK 3
#define CONFIG_SYS_FM2_CLK 3
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
#define CONFIG_SYS_FSL_SRDS_1
@@ -154,21 +154,21 @@
#ifdef CONFIG_ARCH_B4860
#define CONFIG_MAX_DSP_CPUS 12
#define CONFIG_NUM_DSP_CPUS 6
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#else
#define CONFIG_MAX_DSP_CPUS 2
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 0
#endif
#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
@@ -184,8 +184,7 @@
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_T1024)
-#define CONFIG_SYS_FSL_NUM_CC_PLL 2
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 4
@@ -202,15 +201,15 @@
#elif defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_NUM_FMAN 1
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_FSL_SRDS_1
#if defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 4
#define CONFIG_SYS_FSL_SRDS_2
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#endif
#define CONFIG_PME_PLAT_CLK_DIV 1
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
@@ -224,7 +223,7 @@
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2_1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
+#define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000
#endif
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index be55f99030e8..de85bcfdcf96 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -33,7 +33,7 @@ struct srio_liodn_id_table {
{ .id = { id_a }, .num_ids = 1, .portid = port, \
.reg_offset[0] = offsetof(struct ccsr_rio, liodn) \
+ (port - 1) * 0x200 \
- + CONFIG_SYS_FSL_SRIO_ADDR, \
+ + CFG_SYS_FSL_SRIO_ADDR, \
}
struct liodn_id_table {
@@ -130,29 +130,29 @@ extern void fdt_fixup_liodn(void *blob);
#define SET_QMAN_LIODN(liodn) \
SET_LIODN_ENTRY_1("fsl,qman", liodn, \
offsetof(struct ccsr_qman, liodnr) + \
- CONFIG_SYS_FSL_QMAN_OFFSET, \
- CONFIG_SYS_FSL_QMAN_OFFSET)
+ CFG_SYS_FSL_QMAN_OFFSET, \
+ CFG_SYS_FSL_QMAN_OFFSET)
#define SET_BMAN_LIODN(liodn) \
SET_LIODN_ENTRY_1("fsl,bman", liodn, \
offsetof(struct ccsr_bman, liodnr) + \
- CONFIG_SYS_FSL_BMAN_OFFSET, \
- CONFIG_SYS_FSL_BMAN_OFFSET)
+ CFG_SYS_FSL_BMAN_OFFSET, \
+ CFG_SYS_FSL_BMAN_OFFSET)
#define SET_PME_LIODN(liodn) \
SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \
- CONFIG_SYS_FSL_CORENET_PME_OFFSET, \
- CONFIG_SYS_FSL_CORENET_PME_OFFSET)
+ CFG_SYS_FSL_CORENET_PME_OFFSET, \
+ CFG_SYS_FSL_CORENET_PME_OFFSET)
#define SET_PMAN_LIODN(num, liodn) \
SET_LIODN_ENTRY_2("fsl,pman", liodn, 0, \
offsetof(struct ccsr_pman, ppa1) + \
- CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
- CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
+ CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
+ CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
/* -1 from portID due to how immap has the registers */
#define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \
- CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \
+ CFG_SYS_FSL_FM##fmNum##_OFFSET + \
offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1])
#ifdef CONFIG_SYS_FMAN_V3
@@ -160,31 +160,31 @@ extern void fdt_fixup_liodn(void *blob);
#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx", \
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
- CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
+ CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
- CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
+ CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
/* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */
#define SET_FMAN_RX_10G_TYPE2_LIODN(fmNum, enetNum, liodn) \
SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
- CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
+ CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
#else
/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */
#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-1g-rx", \
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
- CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
+ CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-10g-rx", \
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
- CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
+ CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
#endif
/*
* handle both old and new versioned SEC properties:
@@ -193,44 +193,44 @@ extern void fdt_fixup_liodn(void *blob);
#define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \
SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\
offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \
SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
/* This is a bit evil since we treat rtic param as both a string & hex value */
#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
liodnA, \
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
liodnA, \
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, 0)
+ CFG_SYS_FSL_SEC_OFFSET, 0)
#define SET_RAID_ENGINE_JQ_LIODN_ENTRY(jqNum, rNum, liodnA) \
SET_LIODN_ENTRY_1("fsl,raideng-v1.0-job-ring", \
liodnA, \
offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg1) + \
- CONFIG_SYS_FSL_RAID_ENGINE_OFFSET, \
+ CFG_SYS_FSL_RAID_ENGINE_OFFSET, \
offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \
- CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
+ CFG_SYS_FSL_RAID_ENGINE_OFFSET)
#define SET_RMAN_LIODN(ibNum, liodn) \
SET_LIODN_ENTRY_1("fsl,rman-inbound-block", liodn, \
offsetof(struct ccsr_rman, mmitdr) + \
- CONFIG_SYS_FSL_CORENET_RMAN_OFFSET, \
- CONFIG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000)
+ CFG_SYS_FSL_CORENET_RMAN_OFFSET, \
+ CFG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000)
extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
extern struct liodn_id_table raide_liodn_tbl[];
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 0bf5b9c2ba57..8e1820267088 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -862,7 +862,7 @@ struct ccsr_gpio {
};
#define CFG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
-#define CONFIG_SYS_FSL_DDR_ADDR \
+#define CFG_SYS_FSL_DDR_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
#define CFG_SYS_MPC83xx_DMA_OFFSET (0x8000)
#define CFG_SYS_MPC83xx_DMA_ADDR \
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 7a7a7f2113c6..c9ced5474c2c 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -963,7 +963,7 @@ struct rio_lp_serial {
u32 prtoccsr; /* Port Response Time-out CCSR */
u8 res1[20];
u32 pgccsr; /* Port General CSR */
- struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+ struct rio_lp_serial_port port[CFG_SYS_FSL_SRIO_MAX_PORTS];
};
/* Logical error reporting registers */
@@ -993,7 +993,7 @@ struct rio_phys_err_port {
/* Physical error reporting registers */
struct rio_phys_err {
- struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+ struct rio_phys_err_port port[CFG_SYS_FSL_SRIO_MAX_PORTS];
};
/* Implementation Space: General Port-Common */
@@ -1033,7 +1033,7 @@ struct rio_impl_port_spec {
/* Implementation Space: register */
struct rio_implement {
struct rio_impl_common com;
- struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+ struct rio_impl_port_spec port[CFG_SYS_FSL_SRIO_MAX_PORTS];
};
/* Revision Control Register */
@@ -1061,13 +1061,13 @@ struct rio_atmu_riw {
/* ATMU window registers */
struct rio_atmu_win {
- struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
+ struct rio_atmu_row outbw[CFG_SYS_FSL_SRIO_OB_WIN_NUM];
u8 res0[64];
- struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
+ struct rio_atmu_riw inbw[CFG_SYS_FSL_SRIO_IB_WIN_NUM];
};
struct rio_atmu {
- struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+ struct rio_atmu_win port[CFG_SYS_FSL_SRIO_MAX_PORTS];
};
#ifdef CONFIG_SYS_FSL_RMU
@@ -1154,7 +1154,7 @@ struct ccsr_rio {
struct rio_atmu atmu;
#ifdef CONFIG_SYS_FSL_RMU
u8 res5[8192];
- struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
+ struct rio_msg msg[CFG_SYS_FSL_SRIO_MSG_UNIT_NUM];
u8 res6[512];
struct rio_dbell dbell;
u8 res7[100];
@@ -1162,7 +1162,7 @@ struct ccsr_rio {
#endif
#ifdef CONFIG_SYS_FSL_SRIO_LIODN
u8 res5[8192];
- struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+ struct rio_liodn liodn[CFG_SYS_FSL_SRIO_MAX_PORTS];
#endif
};
#endif
@@ -2431,17 +2431,17 @@ struct ccsr_pman {
#endif
#ifdef CONFIG_FSL_CORENET
-#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
+#define CFG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
#ifdef CONFIG_SYS_PMAN
-#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
-#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
-#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
+#define CFG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
+#define CFG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
+#define CFG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
#endif
#define CFG_SYS_MPC8xxx_DDR_OFFSET 0x8000
#define CFG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
#define CFG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
-#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
-#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
+#define CFG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
+#define CFG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
/* In SFPv3, OSPR register is now at offset 0x200.
* * So directly mapping sfp register map to this address */
@@ -2450,13 +2450,13 @@ struct ccsr_pman {
#else
#define CONFIG_SYS_SFP_OFFSET 0xE8000
#endif
-#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
-#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
-#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
-#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
-#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
-#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
-#define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000
+#define CFG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
+#define CFG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
+#define CFG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
+#define CFG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
+#define CFG_SYS_FSL_CPC_OFFSET 0x10000
+#define CFG_SYS_FSL_SCFG_OFFSET 0xFC000
+#define CFG_SYS_FSL_PAMU_OFFSET 0x20000
#define CFG_SYS_MPC85xx_DMA1_OFFSET 0x100000
#define CFG_SYS_MPC85xx_DMA2_OFFSET 0x101000
#define CFG_SYS_MPC85xx_DMA3_OFFSET 0x102000
@@ -2468,7 +2468,7 @@ struct ccsr_pman {
#define CFG_SYS_MPC85xx_GPIO_OFFSET 0x130000
#define CFG_SYS_MPC85xx_TDM_OFFSET 0x185000
#define CFG_SYS_MPC85xx_QE_OFFSET 0x140000
-#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
+#define CFG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
!defined(CONFIG_ARCH_B4420)
#define CFG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
@@ -2487,33 +2487,33 @@ struct ccsr_pman {
#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
#define CFG_SYS_MPC85xx_SATA1_OFFSET 0x220000
#define CFG_SYS_MPC85xx_SATA2_OFFSET 0x221000
-#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x301000
+#define CFG_SYS_FSL_SEC_OFFSET 0x300000
+#define CFG_SYS_FSL_JR0_OFFSET 0x301000
#define CONFIG_SYS_SEC_MON_OFFSET 0x314000
-#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
-#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
-#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
-#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
-#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
-#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
-#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
-#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
-#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
-#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
-#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
-#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
-#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
-#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
-#define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
-#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
-#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
-#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
-#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
-#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
-#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
-#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
-#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
-#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
+#define CFG_SYS_FSL_CORENET_PME_OFFSET 0x316000
+#define CFG_SYS_FSL_QMAN_OFFSET 0x318000
+#define CFG_SYS_FSL_BMAN_OFFSET 0x31a000
+#define CFG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
+#define CFG_SYS_FSL_FM1_OFFSET 0x400000
+#define CFG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
+#define CFG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
+#define CFG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
+#define CFG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
+#define CFG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
+#define CFG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
+#define CFG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
+#define CFG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
+#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
+#define CFG_SYS_FSL_FM2_OFFSET 0x500000
+#define CFG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
+#define CFG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
+#define CFG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
+#define CFG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
+#define CFG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
+#define CFG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
+#define CFG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
+#define CFG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
+#define CFG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
#else
#define CFG_SYS_MPC85xx_ECM_OFFSET 0x0000
#define CFG_SYS_MPC8xxx_DDR_OFFSET 0x2000
@@ -2551,57 +2551,57 @@ struct ccsr_pman {
#define CONFIG_SYS_MDIO1_OFFSET 0x24000
#define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
#if defined(CONFIG_ARCH_C29X)
-#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
+#define CFG_SYS_FSL_SEC_OFFSET 0x80000
+#define CFG_SYS_FSL_JR0_OFFSET 0x81000
#else
-#define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x31000
+#define CFG_SYS_FSL_SEC_OFFSET 0x30000
+#define CFG_SYS_FSL_JR0_OFFSET 0x31000
#endif
#define CFG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
#define CFG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
#define CONFIG_SYS_SEC_MON_OFFSET 0xE6000
#define CONFIG_SYS_SFP_OFFSET 0xE7000
-#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
-#define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
-#define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
-#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
-#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
-#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
+#define CFG_SYS_FSL_QMAN_OFFSET 0x88000
+#define CFG_SYS_FSL_BMAN_OFFSET 0x8a000
+#define CFG_SYS_FSL_FM1_OFFSET 0x100000
+#define CFG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
+#define CFG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
+#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
#endif
#define CFG_SYS_MPC85xx_PIC_OFFSET 0x40000
#define CFG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
-#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
-
-#define CONFIG_SYS_FSL_CPC_ADDR \
- (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
-#define CONFIG_SYS_FSL_SCFG_ADDR \
- (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
-#define CONFIG_SYS_FSL_QMAN_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
-#define CONFIG_SYS_FSL_BMAN_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
-#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
+#define CFG_SYS_FSL_SRIO_OFFSET 0xC0000
+
+#define CFG_SYS_FSL_CPC_ADDR \
+ (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET)
+#define CFG_SYS_FSL_SCFG_ADDR \
+ (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET)
+#define CFG_SYS_FSL_QMAN_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_QMAN_OFFSET)
+#define CFG_SYS_FSL_BMAN_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_BMAN_OFFSET)
+#define CFG_SYS_FSL_CORENET_PME_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_PME_OFFSET)
+#define CFG_SYS_FSL_RAID_ENGINE_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_RAID_ENGINE_OFFSET)
+#define CFG_SYS_FSL_CORENET_RMAN_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_RMAN_OFFSET)
#define CFG_SYS_MPC85xx_GUTS_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GUTS_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
+#define CFG_SYS_FSL_CORENET_CCM_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_CCM_OFFSET)
+#define CFG_SYS_FSL_CORENET_CLK_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_CLK_OFFSET)
+#define CFG_SYS_FSL_CORENET_RCPM_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_RCPM_OFFSET)
#define CFG_SYS_MPC85xx_ECM_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ECM_OFFSET)
-#define CONFIG_SYS_FSL_DDR_ADDR \
+#define CFG_SYS_FSL_DDR_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
-#define CONFIG_SYS_FSL_DDR2_ADDR \
+#define CFG_SYS_FSL_DDR2_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET)
-#define CONFIG_SYS_FSL_DDR3_ADDR \
+#define CFG_SYS_FSL_DDR3_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET)
#define CONFIG_SYS_LBC_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET)
@@ -2631,14 +2631,14 @@ struct ccsr_pman {
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES1_OFFSET)
#define CFG_SYS_MPC85xx_SERDES2_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES2_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
+#define CFG_SYS_FSL_CORENET_SERDES_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES_OFFSET)
+#define CFG_SYS_FSL_CORENET_SERDES2_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES2_OFFSET)
+#define CFG_SYS_FSL_CORENET_SERDES3_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES3_OFFSET)
+#define CFG_SYS_FSL_CORENET_SERDES4_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES4_OFFSET)
#define CFG_SYS_MPC85xx_USB1_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_OFFSET)
#define CFG_SYS_MPC85xx_USB2_ADDR \
@@ -2647,20 +2647,20 @@ struct ccsr_pman {
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_PHY_OFFSET)
#define CFG_SYS_MPC85xx_USB2_PHY_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_PHY_OFFSET)
-#define CONFIG_SYS_FSL_SEC_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
-#define CONFIG_SYS_FSL_FM1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
-#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
-#define CONFIG_SYS_FSL_FM2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
-#define CONFIG_SYS_FSL_SRIO_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
+#define CFG_SYS_FSL_SEC_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_FM1_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_OFFSET)
+#define CFG_SYS_FSL_FM1_DTSEC1_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_DTSEC1_OFFSET)
+#define CFG_SYS_FSL_FM2_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM2_OFFSET)
+#define CFG_SYS_FSL_SRIO_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_SRIO_OFFSET)
#define CONFIG_SYS_PAMU_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET)
#define CONFIG_SYS_PCI1_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI1_OFFSET)
@@ -2739,8 +2739,8 @@ struct ccsr_cluster_l2 {
u32 l2erraddr; /* 0xe54 L2 cache error address */
u32 l2errctl; /* 0xe58 L2 cache error control */
};
-#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
+#define CFG_SYS_FSL_CLUSTER_1_L2 \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CLUSTER_1_L2_OFFSET)
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
diff --git a/board/advantech/imx8mp_rsb3720a1/spl.c b/board/advantech/imx8mp_rsb3720a1/spl.c
index 74dd11545f35..6cc8c23ecf87 100644
--- a/board/advantech/imx8mp_rsb3720a1/spl.c
+++ b/board/advantech/imx8mp_rsb3720a1/spl.c
@@ -129,7 +129,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc0 USDHC1
* mmc1 USDHC2
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(1);
diff --git a/board/advantech/imx8qm_rom7720_a1/spl.c b/board/advantech/imx8qm_rom7720_a1/spl.c
index 5fd60212df9c..22ed63979920 100644
--- a/board/advantech/imx8qm_rom7720_a1/spl.c
+++ b/board/advantech/imx8qm_rom7720_a1/spl.c
@@ -64,7 +64,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
-static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+static struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
{USDHC1_BASE_ADDR, 0, 8},
{USDHC2_BASE_ADDR, 0, 4},
{USDHC3_BASE_ADDR, 0, 4},
@@ -108,7 +108,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc1 USDHC2
* mmc2 USDHC3
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
diff --git a/board/bosch/acc/acc.c b/board/bosch/acc/acc.c
index dbc03c9371fe..770ca8b711b0 100644
--- a/board/bosch/acc/acc.c
+++ b/board/bosch/acc/acc.c
@@ -562,7 +562,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc0 USDHC2
* mmc1 USDHC4
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc2_pads);
diff --git a/board/compulab/cl-som-imx7/cl-som-imx7.c b/board/compulab/cl-som-imx7/cl-som-imx7.c
index 3ee133521860..9733a33ee2c2 100644
--- a/board/compulab/cl-som-imx7/cl-som-imx7.c
+++ b/board/compulab/cl-som-imx7/cl-som-imx7.c
@@ -90,7 +90,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc0 USDHC1
* mmc2 USDHC3 (eMMC)
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
cl_som_imx7_usdhc1_pads_set();
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index c54bffdae450..847ac33ad6b0 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -622,7 +622,7 @@ int board_init(void)
int i;
cm_fx6_set_usdhc_iomux();
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++)
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++)
enable_usdhc_clk(1, i);
}
#endif
diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c
index a50a052df768..e5da91fa282c 100644
--- a/board/congatec/cgtqmx8/cgtqmx8.c
+++ b/board/congatec/cgtqmx8/cgtqmx8.c
@@ -114,7 +114,7 @@ int board_early_init_f(void)
#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
-static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+static struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
{USDHC1_BASE_ADDR, 0, 8},
{USDHC2_BASE_ADDR, 0, 4},
{USDHC3_BASE_ADDR, 0, 4},
@@ -173,7 +173,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc1 (external SD card) USDHC2
* mmc2 (onboard µSD) USDHC3
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
/* onboard eMMC */
diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c
index 733940860f55..f5bed6c35bb3 100644
--- a/board/freescale/common/arm_sleep.c
+++ b/board/freescale/common/arm_sleep.c
@@ -35,7 +35,7 @@ void __weak board_sleep_prepare(void)
bool is_warm_boot(void)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
return 1;
@@ -57,7 +57,7 @@ static void dp_ddr_restore(void)
{
u64 *src, *dst;
int i;
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
/* get the address of ddr date from SPARECR3 */
src = (u64 *)in_le32(&scfg->sparecr[2]);
@@ -71,7 +71,7 @@ static void dp_ddr_restore(void)
void ls1_psci_resume_fixup(void)
{
u32 tmp;
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef QIXIS_BASE
void *qixis_base = (void *)QIXIS_BASE;
@@ -114,7 +114,7 @@ int fsl_dp_resume(void)
{
u32 start_addr;
void (*kernel_resume)(void);
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
if (!is_warm_boot())
return 0;
diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c
index 3bd570a29c9b..d31ad026568b 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -30,7 +30,7 @@
#if defined(CONFIG_MPC85xx)
#define CONFIG_DCFG_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
#else
-#define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR
+#define CONFIG_DCFG_ADDR CFG_SYS_FSL_GUTS_ADDR
#endif
#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c
index bc1b855aaed0..3424d49208fe 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -114,7 +114,7 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
*/
int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
if (memcmp((u8 *)(uintptr_t)csf_hdr_addr,
@@ -130,7 +130,7 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
#if defined(CONFIG_ESBC_HDR_LS)
static int get_ie_info_addr(uintptr_t *ie_addr)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
/* For LS-CH3, the address of IE Table is
* stated in Scratch13 and scratch14 of DCFG.
* Bootrom validates this table while validating uboot.
diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c
index a6ee87da9f55..f754cf42fd38 100644
--- a/board/freescale/common/ls102xa_stream_id.c
+++ b/board/freescale/common/ls102xa_stream_id.c
@@ -9,7 +9,7 @@
void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
{
- void *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ void *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
int i;
u32 icid;
diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c
index ee8ed616cb51..a95d15c1ef39 100644
--- a/board/freescale/common/ns_access.c
+++ b/board/freescale/common/ns_access.c
@@ -180,7 +180,7 @@ static struct csu_ns_dev ns_dev[] = {
void set_devices_ns_access(unsigned long index, u16 val)
{
- u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
+ u32 *base = (u32 *)CFG_SYS_FSL_CSU_ADDR;
u32 *reg;
uint32_t tmp;
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index 3f5f33ebafbe..5ec3f2a76b19 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -539,7 +539,7 @@ int adjust_vdd(ulong vdd_override)
{
int re_enable = disable_interrupts();
#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
#else
ccsr_gur_t __iomem *gur =
(void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c
index b28056bb48b2..bea9ddc99604 100644
--- a/board/freescale/imx8mq_evk/spl.c
+++ b/board/freescale/imx8mq_evk/spl.c
@@ -121,7 +121,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc0 USDHC1
* mmc1 USDHC2
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(0);
diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
index 27f69abf6091..38267acedde1 100644
--- a/board/freescale/ls1012aqds/eth.c
+++ b/board/freescale/ls1012aqds/eth.c
@@ -133,7 +133,7 @@ int pfe_eth_board_init(struct udevice *dev)
struct mii_dev *bus;
static const char *mdio_name;
struct pfe_mdio_info mac_mdio_info;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u8 data8;
struct pfe_eth_dev *priv = dev_get_priv(dev);
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 361bd5c582a2..3f70fbc35659 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -213,7 +213,7 @@ static void fdt_fsl_fixup_of_pfe(void *blob)
struct pfe_prop_val prop_val;
void *l_blob = blob;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
index 565f80059656..5c661274987c 100644
--- a/board/freescale/ls1012ardb/eth.c
+++ b/board/freescale/ls1012ardb/eth.c
@@ -80,7 +80,7 @@ int pfe_eth_board_init(struct udevice *dev)
struct mii_dev *bus;
struct pfe_mdio_info mac_mdio_info;
struct pfe_eth_dev *priv = dev_get_priv(dev);
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
int srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c
index 3ed6100b7cf0..8605d064138a 100644
--- a/board/freescale/ls1021aiot/ls1021aiot.c
+++ b/board/freescale/ls1021aiot/ls1021aiot.c
@@ -38,7 +38,7 @@ int checkboard(void)
puts("Board: LS1021AIOT\n");
#ifndef CONFIG_QSPI_BOOT
- struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur *dcfg = (struct ccsr_gur *)CFG_SYS_FSL_GUTS_ADDR;
u32 cpldrev;
cpldrev = in_be32(&dcfg->gpporcr1);
@@ -51,7 +51,7 @@ int checkboard(void)
void ddrmc_init(void)
{
- struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR;
u32 temp_sdram_cfg, tmp;
out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
@@ -111,7 +111,7 @@ int dram_init(void)
int board_early_init_f(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET
/* clear BD & FR bits for BE BD's and frame data */
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 2eaad9e74249..d0674d014ac5 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -160,7 +160,7 @@ int dram_init(void)
int board_early_init_f(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET
/* clear BD & FR bits for BE BD's and frame data */
@@ -185,7 +185,7 @@ int board_early_init_f(void)
void board_init_f(ulong dummy)
{
#ifdef CONFIG_NAND_BOOT
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 porsr1, pinctl;
/*
@@ -234,7 +234,7 @@ void board_init_f(ulong dummy)
void config_etseccm_source(int etsec_gtx_125_mux)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
switch (etsec_gtx_125_mux) {
case GE0_CLK125:
@@ -308,7 +308,7 @@ int config_board_mux(int ctrl_type)
int config_serdes_mux(void)
{
- struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur *gur = (struct ccsr_gur *)CFG_SYS_FSL_GUTS_ADDR;
u32 cfg;
cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c
index f016088670f6..d95eb734c2d2 100644
--- a/board/freescale/ls1021atsn/ls1021atsn.c
+++ b/board/freescale/ls1021atsn/ls1021atsn.c
@@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR;
static void ddrmc_init(void)
{
#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
- struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR;
u32 temp_sdram_cfg, tmp;
out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
@@ -130,7 +130,7 @@ int board_eth_init(struct bd_info *bis)
int board_early_init_f(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET
/*
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 746b35a678b0..119ae17a2c6c 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -143,7 +143,7 @@ int checkboard(void)
void ddrmc_init(void)
{
- struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR;
u32 temp_sdram_cfg, tmp;
out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
@@ -288,7 +288,7 @@ static void convert_serdes_mux(int type, int need_reset)
int config_serdes_mux(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
@@ -383,7 +383,7 @@ conflict:
int board_early_init_f(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET
/* clear BD & FR bits for BE BD's and frame data */
diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c
index 7bfbacde4fbd..6783ebebb59e 100644
--- a/board/freescale/ls1043aqds/eth.c
+++ b/board/freescale/ls1043aqds/eth.c
@@ -261,7 +261,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
void fdt_fixup_board_enet(void *fdt)
{
int i;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &
@@ -302,7 +302,7 @@ int board_eth_init(struct bd_info *bis)
int i, idx, lane, slot, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index 7ac2c1ae901d..b02f649910f6 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -430,9 +430,9 @@ void board_retimer_init(void)
int board_early_init_f(void)
{
- u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+ u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR;
#ifdef CONFIG_HAS_FSL_XHCI_USB
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
#endif
#ifdef CONFIG_LPUART
@@ -475,7 +475,7 @@ int board_early_init_f(void)
bool is_warm_boot(void)
{
#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
return 1;
@@ -529,7 +529,7 @@ int board_init(void)
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
board_retimer_init();
-#ifdef CONFIG_SYS_FSL_SERDES
+#ifdef CFG_SYS_FSL_SERDES
config_serdes_mux();
#endif
@@ -596,6 +596,6 @@ u16 flash_read16(void *addr)
#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
void *env_sf_get_env_addr(void)
{
- return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
+ return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
}
#endif
diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c
index fa59116ce57b..00ff6028e69f 100644
--- a/board/freescale/ls1043ardb/eth.c
+++ b/board/freescale/ls1043ardb/eth.c
@@ -21,7 +21,7 @@ int board_eth_init(struct bd_info *bis)
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
u32 srds_s1;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index 8c91f0771fbe..799900e9c949 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -188,7 +188,7 @@ int checkboard(void)
int board_init(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315();
@@ -230,7 +230,7 @@ int board_init(void)
int config_board_mux(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
if (hwconfig("qe-hdlc")) {
diff --git a/board/freescale/ls1046afrwy/eth.c b/board/freescale/ls1046afrwy/eth.c
index 06ccfe9e8ed5..71c4c21cd4fd 100644
--- a/board/freescale/ls1046afrwy/eth.c
+++ b/board/freescale/ls1046afrwy/eth.c
@@ -20,7 +20,7 @@ int board_eth_init(struct bd_info *bis)
struct memac_mdio_info dtsec_mdio_info;
struct mii_dev *dev;
u32 srds_s1;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
@@ -70,7 +70,7 @@ int fdt_update_ethernet_dt(void *blob)
int i, prop;
int offset, nodeoff;
const char *path;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c
index 5a298cd311e4..f6e5c122ead6 100644
--- a/board/freescale/ls1046afrwy/ls1046afrwy.c
+++ b/board/freescale/ls1046afrwy/ls1046afrwy.c
@@ -146,7 +146,7 @@ int board_setup_core_volt(u32 vdd)
void config_board_mux(void)
{
#ifdef CONFIG_HAS_FSL_XHCI_USB
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
/*
* USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT
diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c
index 13207a1a37d5..88265a399487 100644
--- a/board/freescale/ls1046aqds/eth.c
+++ b/board/freescale/ls1046aqds/eth.c
@@ -268,7 +268,7 @@ int board_eth_init(struct bd_info *bis)
{
int i, idx, lane, slot, interface;
struct memac_mdio_info dtsec_mdio_info;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1, srds_s2;
u8 brdcfg12;
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index aa6e30e6b2a6..dfdc9f06ab14 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -300,9 +300,9 @@ int i2c_multiplexer_select_vid_channel(u8 channel)
int board_early_init_f(void)
{
- u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+ u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR;
#ifdef CONFIG_HAS_FSL_XHCI_USB
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
#endif
#ifdef CONFIG_LPUART
@@ -347,7 +347,7 @@ int board_early_init_f(void)
bool is_warm_boot(void)
{
#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
return 1;
@@ -395,7 +395,7 @@ int board_init(void)
{
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
-#ifdef CONFIG_SYS_FSL_SERDES
+#ifdef CFG_SYS_FSL_SERDES
config_serdes_mux();
#endif
@@ -479,6 +479,6 @@ u16 flash_read16(void *addr)
#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
void *env_sf_get_env_addr(void)
{
- return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
+ return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
}
#endif
diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c
index a3e147a48b98..04fa57f81b29 100644
--- a/board/freescale/ls1046ardb/eth.c
+++ b/board/freescale/ls1046ardb/eth.c
@@ -22,7 +22,7 @@ int board_eth_init(struct bd_info *bis)
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
u32 srds_s1;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
@@ -84,7 +84,7 @@ int fdt_update_ethernet_dt(void *blob)
int i, prop;
int offset, nodeoff;
const char *path;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c
index 05269fccd6ab..1d12d9189b78 100644
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ b/board/freescale/ls1046ardb/ls1046ardb.c
@@ -80,7 +80,7 @@ int checkboard(void)
int board_init(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_NXP_ESBC
/*
@@ -146,7 +146,7 @@ int power_init_board(void)
void config_board_mux(void)
{
#ifdef CONFIG_HAS_FSL_XHCI_USB
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
/* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */
diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c
index 140733de6af0..8fe643f70b96 100644
--- a/board/freescale/ls1088a/eth_ls1088aqds.c
+++ b/board/freescale/ls1088a/eth_ls1088aqds.c
@@ -471,7 +471,7 @@ static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval)
*/
static void initialize_dpmac_to_slot(void)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 serdes1_prtcl, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
@@ -524,7 +524,7 @@ static void initialize_dpmac_to_slot(void)
void ls1088a_handle_phy_interface_sgmii(int dpmac_id)
{
struct mii_dev *bus;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 serdes1_prtcl, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
@@ -576,7 +576,7 @@ void ls1088a_handle_phy_interface_sgmii(int dpmac_id)
void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)
{
struct mii_dev *bus;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 serdes1_prtcl, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
@@ -615,7 +615,7 @@ void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)
void ls1088a_handle_phy_interface_xsgmii(int i)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 serdes1_prtcl, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
@@ -639,7 +639,7 @@ void ls1088a_handle_phy_interface_xsgmii(int i)
static void ls1088a_handle_phy_interface_rgmii(int dpmac_id)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 serdes1_prtcl, cfg;
struct mii_dev *bus;
@@ -682,7 +682,7 @@ int board_eth_init(struct bd_info *bis)
sizeof(struct memac_mdio_info));
memac_mdio0_info->regs =
(struct memac_mdio_controller *)
- CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ CFG_SYS_FSL_WRIOP1_MDIO1;
memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the real MDIO1 bus */
@@ -807,7 +807,7 @@ static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
int board_fit_config_name_match(const char *name)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
char expected_dts[100];
char srds_s1_str[2];
u32 srds_s1, cfg;
diff --git a/board/freescale/ls1088a/eth_ls1088ardb.c b/board/freescale/ls1088a/eth_ls1088ardb.c
index 1ba5e94d0a0a..5792070f9394 100644
--- a/board/freescale/ls1088a/eth_ls1088ardb.c
+++ b/board/freescale/ls1088a/eth_ls1088ardb.c
@@ -25,7 +25,7 @@ int board_eth_init(struct bd_info *bis)
int i, interface;
struct memac_mdio_info mdio_info;
struct mii_dev *dev;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct memac_mdio_controller *reg;
u32 srds_s1, cfg;
@@ -35,14 +35,14 @@ int board_eth_init(struct bd_info *bis)
srds_s1 = serdes_get_number(FSL_SRDS_1, cfg);
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the EMI 1 */
fm_memac_mdio_init(bis, &mdio_info);
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index 0157377354a5..ae81740dc36c 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -1031,7 +1031,7 @@ int is_flash_available(void)
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
void *env_sf_get_env_addr(void)
{
- return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
+ return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
}
#endif
#endif
diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index 7db37898220a..6da6e5c84152 100644
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -502,7 +502,7 @@ static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
*/
static void initialize_dpmac_to_slot(void)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
@@ -656,7 +656,7 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
{
int lane, slot;
struct mii_dev *bus;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
@@ -799,7 +799,7 @@ void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
{
int lane = 0, slot;
struct mii_dev *bus;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
@@ -864,7 +864,7 @@ void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
void ls2080a_handle_phy_interface_xsgmii(int i)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
@@ -898,7 +898,7 @@ int board_eth_init(struct bd_info *bis)
{
#ifndef CONFIG_DM_ETH
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
@@ -920,7 +920,7 @@ int board_eth_init(struct bd_info *bis)
sizeof(struct memac_mdio_info));
memac_mdio0_info->regs =
(struct memac_mdio_controller *)
- CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ CFG_SYS_FSL_WRIOP1_MDIO1;
memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the real MDIO1 bus */
@@ -930,7 +930,7 @@ int board_eth_init(struct bd_info *bis)
sizeof(struct memac_mdio_info));
memac_mdio1_info->regs =
(struct memac_mdio_controller *)
- CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ CFG_SYS_FSL_WRIOP1_MDIO2;
memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
/* Register the real MDIO2 bus */
@@ -1053,7 +1053,7 @@ static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
int board_fit_config_name_match(const char *name)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 rcw_status = in_le32(&gur->rcwsr[28]);
char srds_s1_str[2], srds_s2_str[2];
u32 srds_s1, srds_s2;
diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c
index 21b4c16ff27c..7034bc6e5d21 100644
--- a/board/freescale/ls2080ardb/eth_ls2080rdb.c
+++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c
@@ -29,7 +29,7 @@ int board_eth_init(struct bd_info *bis)
int i, interface;
struct memac_mdio_info mdio_info;
struct mii_dev *dev;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1;
struct memac_mdio_controller *reg;
@@ -37,14 +37,14 @@ int board_eth_init(struct bd_info *bis)
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the EMI 1 */
fm_memac_mdio_init(bis, &mdio_info);
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index fb0699cb94ff..aa2d65b45b89 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -242,7 +242,7 @@ int config_board_mux(int ctrl_type)
ulong *cs4340_get_fw_addr(void)
{
#ifdef CONFIG_TFABOOT
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr);
#endif
ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR;
@@ -318,7 +318,7 @@ int misc_init_r(void)
char *env_hwconfig;
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
u32 val;
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr);
val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c b/board/freescale/lx2160a/eth_lx2160aqds.c
index 1819b27561ed..374d0526b42f 100644
--- a/board/freescale/lx2160a/eth_lx2160aqds.c
+++ b/board/freescale/lx2160a/eth_lx2160aqds.c
@@ -459,7 +459,7 @@ int board_eth_init(struct bd_info *bis)
size_t len;
struct mii_dev *bus;
const struct phy_config *phy_config;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1, srds_s2, srds_s3;
srds_s1 = in_le32(&gur->rcwsr[28]) &
@@ -476,14 +476,14 @@ int board_eth_init(struct bd_info *bis)
sprintf(srds, "%d_%d_%d", srds_s1, srds_s2, srds_s3);
- regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ regs = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = regs;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/*Register the EMI 1*/
fm_memac_mdio_init(bis, &mdio_info);
- regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ regs = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = regs;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
@@ -670,9 +670,9 @@ int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
priv->realbusnum, priv->ioslot);
if (priv->realbusnum == EMI1)
- reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ reg = CFG_SYS_FSL_WRIOP1_MDIO1;
else
- reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ reg = CFG_SYS_FSL_WRIOP1_MDIO2;
offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
if (offset < 0) {
@@ -929,7 +929,7 @@ static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
int board_fit_config_name_match(const char *name)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 rcw_status = in_le32(&gur->rcwsr[28]);
char srds_s1_str[2], srds_s2_str[2], srds_s3_str[2];
u32 srds_s1, srds_s2, srds_s3;
diff --git a/board/freescale/lx2160a/eth_lx2160ardb.c b/board/freescale/lx2160a/eth_lx2160ardb.c
index 15cbc58d59a7..8a9c60f46cd5 100644
--- a/board/freescale/lx2160a/eth_lx2160ardb.c
+++ b/board/freescale/lx2160a/eth_lx2160ardb.c
@@ -48,21 +48,21 @@ int board_eth_init(struct bd_info *bis)
struct memac_mdio_controller *reg;
int i, interface;
struct mii_dev *dev;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the EMI 1 */
fm_memac_mdio_init(bis, &mdio_info);
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
diff --git a/board/freescale/lx2160a/eth_lx2162aqds.c b/board/freescale/lx2160a/eth_lx2162aqds.c
index ac6218ebe4ac..25fee899618f 100644
--- a/board/freescale/lx2160a/eth_lx2162aqds.c
+++ b/board/freescale/lx2160a/eth_lx2162aqds.c
@@ -480,7 +480,7 @@ int board_eth_init(struct bd_info *bis)
size_t len;
struct mii_dev *bus;
const struct phy_config *phy_config;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1, srds_s2;
srds_s1 = in_le32(&gur->rcwsr[28]) &
@@ -493,14 +493,14 @@ int board_eth_init(struct bd_info *bis)
sprintf(srds, "%d_%d", srds_s1, srds_s2);
- regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ regs = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = regs;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/*Register the EMI 1*/
fm_memac_mdio_init(bis, &mdio_info);
- regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ regs = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = regs;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
@@ -679,9 +679,9 @@ int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
priv->realbusnum, priv->ioslot);
if (priv->realbusnum == EMI1)
- reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ reg = CFG_SYS_FSL_WRIOP1_MDIO1;
else
- reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ reg = CFG_SYS_FSL_WRIOP1_MDIO2;
offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
if (offset < 0) {
@@ -946,7 +946,7 @@ static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
int board_fit_config_name_match(const char *name)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 rcw_status = in_le32(&gur->rcwsr[28]);
char srds_s1_str[2], srds_s2_str[2];
u32 srds_s1, srds_s2;
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 5f0cc9eb7e9e..437675517ebd 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -180,7 +180,7 @@ void esdhc_dspi_status_fixup(void *blob)
const char dspi1_path[] = "/soc/spi at 2110000";
const char dspi2_path[] = "/soc/spi at 2120000";
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 sdhc1_base_pmux;
u32 sdhc2_base_pmux;
u32 iic5_pmux;
@@ -385,7 +385,7 @@ static void esdhc_adapter_card_ident(void)
int config_board_mux(void)
{
u8 reg11, reg5, reg13;
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 sdhc1_base_pmux;
u32 sdhc2_base_pmux;
u32 iic5_pmux;
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index a9800ed7698f..4f27d3e8ecce 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -124,7 +124,7 @@ static int power_init(void)
return ret;
}
- if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
+ if (!i2c_probe(CFG_SYS_FSL_PMIC_I2C_ADDR)) {
ret = pmic_init(I2C_0);
if (ret)
return ret;
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index 859ffc4935c8..1b1263091e50 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -167,7 +167,7 @@ unsigned long get_board_sys_clk(void)
int misc_init_r(void)
{
- serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
u32 actual[NUM_SRDS_BANKS];
unsigned int i;
u8 sw;
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
index dd1c35fa2015..555985b6f251 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -192,7 +192,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_TARGET_T2080QDS
serdes_corenet_t *srds_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
#endif
u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
diff --git a/board/google/imx8mq_phanbell/spl.c b/board/google/imx8mq_phanbell/spl.c
index eec3f3d931b2..83de5bfd75fa 100644
--- a/board/google/imx8mq_phanbell/spl.c
+++ b/board/google/imx8mq_phanbell/spl.c
@@ -97,7 +97,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc0 USDHC1
* mmc1 USDHC2
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(0);
diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c
index 758bd5b79ba1..6a1711092b62 100644
--- a/board/keymile/kmcent2/kmcent2.c
+++ b/board/keymile/kmcent2/kmcent2.c
@@ -220,7 +220,7 @@ EVENT_SPY(EVT_MISC_INIT_F, kmcent2_misc_init_f);
int misc_init_r(void)
{
- serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_MPC85xx_SCFG;
ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CFG_SYS_MPC85xx_GUTS_ADDR;
diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
index ed8142d868f9..3719bcf7317e 100644
--- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
+++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
@@ -50,8 +50,8 @@ int dram_init(void)
int board_early_init_f(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
/* Disable unused MCK1 */
diff --git a/board/kontron/pitx_imx8m/spl.c b/board/kontron/pitx_imx8m/spl.c
index ef3256898de6..f6fd17048d04 100644
--- a/board/kontron/pitx_imx8m/spl.c
+++ b/board/kontron/pitx_imx8m/spl.c
@@ -132,7 +132,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc0 USDHC1
* mmc1 USDHC2
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(0);
diff --git a/board/kontron/sl-mx6ul/spl.c b/board/kontron/sl-mx6ul/spl.c
index 3ae8bf620949..bae0e70a657d 100644
--- a/board/kontron/sl-mx6ul/spl.c
+++ b/board/kontron/sl-mx6ul/spl.c
@@ -105,7 +105,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc0 USDHC1
* mmc1 USDHC2
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
diff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c
index 56eae3b4e9ee..b1f6881275d5 100644
--- a/board/liebherr/mccmon6/spl.c
+++ b/board/liebherr/mccmon6/spl.c
@@ -539,7 +539,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc0 Soldered on board eMMC device
* mmc1 MicroSD card
*/
- for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+ for (index = 0; index < CFG_SYS_FSL_USDHC_NUM; ++index) {
switch (index) {
case 0:
SETUP_IOMUX_PADS(usdhc3_pads);
@@ -554,7 +554,7 @@ int board_mmc_init(struct bd_info *bis)
break;
default:
printf("Warning: More USDHC controllers (%d) than supported (%d)\n",
- index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ index + 1, CFG_SYS_FSL_USDHC_NUM);
return -EINVAL;
}
diff --git a/board/myir/mys_6ulx/spl.c b/board/myir/mys_6ulx/spl.c
index 5cd4d0528309..3cf14e2bc660 100644
--- a/board/myir/mys_6ulx/spl.c
+++ b/board/myir/mys_6ulx/spl.c
@@ -155,7 +155,7 @@ int board_mmc_init(struct bd_info *bis)
{
int i, ret;
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc1_pads);
diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c
index fea4aa33655a..b6d459fdfce6 100644
--- a/board/phytec/pcl063/spl.c
+++ b/board/phytec/pcl063/spl.c
@@ -156,7 +156,7 @@ int board_mmc_init(struct bd_info *bis)
{
int i, ret;
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc1_pads);
diff --git a/board/purism/librem5/spl.c b/board/purism/librem5/spl.c
index a068f76460d8..1bfd948806f2 100644
--- a/board/purism/librem5/spl.c
+++ b/board/purism/librem5/spl.c
@@ -204,7 +204,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc0 USDHC1
* mmc1 USDHC2
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
log_debug("Initializing FSL USDHC port %d\n", i);
switch (i) {
case 0:
diff --git a/board/ronetix/imx8mq-cm/spl.c b/board/ronetix/imx8mq-cm/spl.c
index c32a06f12706..b9a67451aecc 100644
--- a/board/ronetix/imx8mq-cm/spl.c
+++ b/board/ronetix/imx8mq-cm/spl.c
@@ -89,7 +89,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc0 USDHC1
* mmc1 USDHC2
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(0);
diff --git a/board/seeed/npi_imx6ull/spl.c b/board/seeed/npi_imx6ull/spl.c
index 4b56f52d985b..b29da2c1fc1e 100644
--- a/board/seeed/npi_imx6ull/spl.c
+++ b/board/seeed/npi_imx6ull/spl.c
@@ -154,7 +154,7 @@ int board_mmc_init(struct bd_info *bis)
{
int i, ret;
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc1_pads);
diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c
index d358a209a4a3..04527cf79ab2 100644
--- a/board/socrates/sdram.c
+++ b/board/socrates/sdram.c
@@ -26,7 +26,7 @@
phys_size_t fixed_sdram(void)
{
struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+ (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
/*
* Disable memory controller.
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index 8d2642f25d08..96d0185329d2 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -322,7 +322,7 @@ int board_ehci_hcd_init(int port)
#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
/* use the following sequence: eMMC, MMC1, SD1 */
-struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
{USDHC3_BASE_ADDR},
{USDHC1_BASE_ADDR},
{USDHC2_BASE_ADDR},
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index ab2ab587ffb6..475250d8013a 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -290,7 +290,7 @@ int board_ehci_hcd_init(int port)
#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
/* use the following sequence: eMMC, MMC */
-struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
{USDHC3_BASE_ADDR},
{USDHC1_BASE_ADDR},
};
diff --git a/board/traverse/ten64/ten64.c b/board/traverse/ten64/ten64.c
index a15b81b0cfdc..e6403cad1f51 100644
--- a/board/traverse/ten64/ten64.c
+++ b/board/traverse/ten64/ten64.c
@@ -61,7 +61,7 @@ int board_early_init_f(void)
static u32 ten64_get_board_rev(void)
{
- struct ccsr_gur *dcfg = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur *dcfg = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 board_rev_in = in_le32(&dcfg->gpporcr1);
return board_rev_in;
}
diff --git a/board/variscite/dart_6ul/spl.c b/board/variscite/dart_6ul/spl.c
index 91d470f6e5e2..17b1ae748846 100644
--- a/board/variscite/dart_6ul/spl.c
+++ b/board/variscite/dart_6ul/spl.c
@@ -159,7 +159,7 @@ int board_mmc_init(struct bd_info *bis)
{
int i, ret;
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc1_pads);
diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c
index 0983d1005881..717e02a039b7 100644
--- a/board/wandboard/spl.c
+++ b/board/wandboard/spl.c
@@ -487,7 +487,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc0 SOM MicroSD
* mmc1 Carrier board MicroSD
*/
- for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+ for (index = 0; index < CFG_SYS_FSL_USDHC_NUM; ++index) {
switch (index) {
case 0:
SETUP_IOMUX_PADS(usdhc3_pads);
@@ -504,7 +504,7 @@ int board_mmc_init(struct bd_info *bis)
default:
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
- index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ index + 1, CFG_SYS_FSL_USDHC_NUM);
return -EINVAL;
}
diff --git a/cmd/blob.c b/cmd/blob.c
index e2efae7a1159..7c77c410d528 100644
--- a/cmd/blob.c
+++ b/cmd/blob.c
@@ -84,7 +84,7 @@ static int do_blob(struct cmd_tbl *cmdtp, int flag, int argc,
hab_caam_clock_enable(1);
- u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR +
+ u32 out_jr_size = sec_in32(CFG_SYS_FSL_JR0_ADDR +
FSL_CAAM_ORSR_JRa_OFFSET);
if (out_jr_size != FSL_CAAM_MAX_JR_SIZE)
sec_init();
diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c
index 542b1652d80d..d32c1fe5c31a 100644
--- a/drivers/crypto/fsl/jobdesc.c
+++ b/drivers/crypto/fsl/jobdesc.c
@@ -28,7 +28,7 @@ uint32_t secmem_set_cmd(uint32_t sec_mem_cmd)
{
uint32_t temp_reg;
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
uint32_t sm_vid = SM_VERSION(sec_in32(&sec->smvid));
uint32_t jr_id = 0;
@@ -58,7 +58,7 @@ int caam_page_alloc(uint8_t page_num, uint8_t partition_num)
{
uint32_t temp_reg;
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
uint32_t sm_vid = SM_VERSION(sec_in32(&sec->smvid));
uint32_t jr_id = 0;
@@ -116,7 +116,7 @@ int caam_page_alloc(uint8_t page_num, uint8_t partition_num)
int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt,
uint8_t *dek_blob, uint32_t in_sz)
{
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
uint32_t sm_vid = SM_VERSION(sec_in32(&sec->smvid));
uint32_t jr_id = 0;
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 8c0fb27b5322..ee822edd6c8e 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -33,8 +33,8 @@
uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
0,
#if defined(CONFIG_ARCH_C29X)
- CONFIG_SYS_FSL_SEC_IDX_OFFSET,
- 2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
+ CFG_SYS_FSL_SEC_IDX_OFFSET,
+ 2 * CFG_SYS_FSL_SEC_IDX_OFFSET
#endif
};
@@ -42,11 +42,11 @@ uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
struct udevice *caam_dev;
#else
#define SEC_ADDR(idx) \
- (ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
+ (ulong)((CFG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
#define SEC_JR0_ADDR(idx) \
(ulong)(SEC_ADDR(idx) + \
- (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+ (CFG_SYS_FSL_JR0_OFFSET - CFG_SYS_FSL_SEC_OFFSET))
struct caam_regs caam_st;
#endif
diff --git a/drivers/crypto/fsl/sec.c b/drivers/crypto/fsl/sec.c
index f0a4a63d8863..9de30a6112fa 100644
--- a/drivers/crypto/fsl/sec.c
+++ b/drivers/crypto/fsl/sec.c
@@ -128,7 +128,7 @@ u8 caam_get_era(void)
{0x0A1C, 1, 5}
};
- ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t __iomem *sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
u32 secvid_ms = sec_in32(&sec->secvid_ms);
u32 ccbvid = sec_in32(&sec->ccbvid);
u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >>
diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index 629ba6784e0d..5e8fb7a89c21 100644
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -40,16 +40,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
switch (ctrl_num) {
case 0:
- ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
- ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
- ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 0b0b4e5cb7ee..df7ec484651a 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -2590,7 +2590,7 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
void erratum_a009942_check_cpo(void)
{
struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+ (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
u32 cpo, cpo_e, cpo_o, cpo_target, cpo_optimal;
u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24;
u32 cpo_max = cpo_min;
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 89cb4d352eed..3c1f7a189120 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -86,16 +86,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
#endif
switch (ctrl_num) {
case 0:
- ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
- ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
- ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
diff --git a/drivers/ddr/fsl/fsl_mmdc.c b/drivers/ddr/fsl/fsl_mmdc.c
index cbd625b7eeac..28f2219b2a43 100644
--- a/drivers/ddr/fsl/fsl_mmdc.c
+++ b/drivers/ddr/fsl/fsl_mmdc.c
@@ -28,7 +28,7 @@ static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
void mmdc_init(const struct fsl_mmdc_info *priv)
{
- struct mmdc_regs *mmdc = (struct mmdc_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct mmdc_regs *mmdc = (struct mmdc_regs *)CFG_SYS_FSL_DDR_ADDR;
unsigned int tmp;
/* 1. set configuration request */
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index ed3313a53151..fcff223b4f0d 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -21,18 +21,18 @@
#include <asm/bitops.h>
/*
- * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
+ * CFG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
* of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
* all Power SoCs. But it could be different for ARM SoCs. For example,
* fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
* 0x00_8000_0000 ~ 0x00_ffff_ffff
* 0x80_8000_0000 ~ 0xff_ffff_ffff
*/
-#ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+#ifndef CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
#ifdef CONFIG_MPC83xx
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
#else
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
#endif
#endif
@@ -898,7 +898,7 @@ phys_size_t fsl_ddr_sdram(void)
/* Reset info structure. */
memset(&info, 0, sizeof(fsl_ddr_info_t));
- info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
+ info.mem_base = CFG_SYS_FSL_DDR_SDRAM_BASE_PHY;
info.first_ctrl = 0;
info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
@@ -946,7 +946,7 @@ fsl_ddr_sdram_size(void)
unsigned long long total_memory = 0;
memset(&info, 0 , sizeof(fsl_ddr_info_t));
- info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
+ info.mem_base = CFG_SYS_FSL_DDR_SDRAM_BASE_PHY;
info.first_ctrl = 0;
info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
index 9c2ddeaf932f..0f1e99eeb039 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
@@ -18,7 +18,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
{
unsigned int i;
struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
+ (struct ccsr_ddr __iomem *)CFG_SYS_FSL_DDR_ADDR;
if (ctrl_num != 0) {
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
@@ -71,7 +71,7 @@ void
ddr_enable_ecc(unsigned int dram_size)
{
struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+ (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
index 9ed80d63ef05..b830e7cbd141 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
@@ -18,7 +18,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
{
unsigned int i;
struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
+ (struct ccsr_ddr __iomem *)CFG_SYS_FSL_DDR_ADDR;
#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 47339c59737a..0f2dc243cb82 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -52,16 +52,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
switch (ctrl_num) {
case 0:
- ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
- ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
- ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index 43cb01804b71..fd8c2dd1a9ca 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -34,16 +34,16 @@ u32 fsl_ddr_get_version(unsigned int ctrl_num)
switch (ctrl_num) {
case 0:
- ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
- ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
- ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
@@ -181,7 +181,7 @@ u32 fsl_ddr_get_intl3r(void)
void print_ddr_info(unsigned int start_ctrl)
{
struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+ (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
#if defined(CONFIG_E6500) && (CONFIG_SYS_NUM_DDR_CTLRS == 3)
u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
@@ -195,14 +195,14 @@ void print_ddr_info(unsigned int start_ctrl)
#if CONFIG_SYS_NUM_DDR_CTLRS >= 2
if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
(start_ctrl == 1)) {
- ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr = (void __iomem *)CFG_SYS_FSL_DDR2_ADDR;
sdram_cfg = ddr_in32(&ddr->sdram_cfg);
}
#endif
#if CONFIG_SYS_NUM_DDR_CTLRS >= 3
if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
(start_ctrl == 2)) {
- ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr = (void __iomem *)CFG_SYS_FSL_DDR3_ADDR;
sdram_cfg = ddr_in32(&ddr->sdram_cfg);
}
#endif
@@ -353,16 +353,16 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
for (i = first_ctrl; i <= last_ctrl; i++) {
switch (i) {
case 0:
- ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
- ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
- ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
diff --git a/drivers/misc/fsl_devdis.c b/drivers/misc/fsl_devdis.c
index cfe03b40cd01..179053a298af 100644
--- a/drivers/misc/fsl_devdis.c
+++ b/drivers/misc/fsl_devdis.c
@@ -14,7 +14,7 @@
void device_disable(const struct devdis_table *tbl, uint32_t num)
{
int i;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
/*
* Extract hwconfig from environment and disable unused device.
diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
index 59df57a9acc7..30a9409e5ab2 100644
--- a/drivers/misc/fsl_portals.c
+++ b/drivers/misc/fsl_portals.c
@@ -28,7 +28,7 @@ void setup_qbman_portals(void)
CONFIG_SYS_BMAN_SWP_ISDR_REG;
void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
CONFIG_SYS_QMAN_SWP_ISDR_REG;
- struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
+ struct ccsr_qman *qman = (void *)CFG_SYS_FSL_QMAN_ADDR;
/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
#ifdef CONFIG_PHYS_64BIT
@@ -159,7 +159,7 @@ static int fdt_qportal(void *blob, int off, int id, char *name,
if (!strncmp(name, "pme", 3)) {
u32 pme_rev1, pme_rev2;
ccsr_pme_t *pme_regs =
- (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
+ (void *)CFG_SYS_FSL_CORENET_PME_ADDR;
pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1);
pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2);
@@ -190,7 +190,7 @@ void fdt_fixup_qportals(void *blob)
int off, err;
unsigned int maj, min;
unsigned int ip_cfg;
- struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
+ struct ccsr_qman *qman = (void *)CFG_SYS_FSL_QMAN_ADDR;
u32 rev_1 = in_be32(&qman->ip_rev_1);
u32 rev_2 = in_be32(&qman->ip_rev_2);
char compat[64];
@@ -302,7 +302,7 @@ void fdt_fixup_bportals(void *blob)
int off, err;
unsigned int maj, min;
unsigned int ip_cfg;
- struct ccsr_bman *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR;
+ struct ccsr_bman *bman = (void *)CFG_SYS_FSL_BMAN_ADDR;
u32 rev_1 = in_be32(&bman->ip_rev_1);
u32 rev_2 = in_be32(&bman->ip_rev_2);
char compat[64];
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index ca5a87969f88..d5066666698c 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -988,7 +988,7 @@ int fsl_esdhc_mmc_init(struct bd_info *bis)
struct fsl_esdhc_cfg *cfg;
cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
- cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+ cfg->esdhc_base = CFG_SYS_FSL_ESDHC_ADDR;
cfg->max_bus_width = CONFIG_SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH;
/* Prefer peripheral clock which provides higher frequency. */
if (gd->arch.sdhc_per_clk)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 92b152fc9794..5ee3ce782313 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -1351,7 +1351,7 @@ int fsl_esdhc_mmc_init(struct bd_info *bis)
struct fsl_esdhc_cfg *cfg;
cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
- cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+ cfg->esdhc_base = CFG_SYS_FSL_ESDHC_ADDR;
cfg->sdhc_clk = gd->arch.sdhc_clk;
return fsl_esdhc_initialize(bis, cfg);
}
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 1ffe9e2b7a58..c23e0c07702f 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -125,7 +125,7 @@ qsgmii_loop:
static void dtsec_init_phy(struct fm_eth *fm_eth)
{
#ifndef CONFIG_SYS_FMAN_V3
- struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
+ struct dtsec *regs = (struct dtsec *)CFG_SYS_FSL_FM1_DTSEC1_ADDR;
/* Assign a Physical address to the TBI */
out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index ee96abbf77f3..9b6dbe2882fd 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -403,7 +403,7 @@ int fm_init_common(int index, struct ccsr_fman *reg)
} else {
ret = spi_flash_read(ucode_flash,
CONFIG_SYS_FMAN_FW_ADDR +
- CONFIG_SYS_FSL_QSPI_BASE,
+ CFG_SYS_FSL_QSPI_BASE,
CONFIG_SYS_QE_FMAN_FW_LENGTH,
addr);
if (ret)
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index af94dabe291e..5cfed425a42b 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -92,7 +92,7 @@ int fm_standard_init(struct bd_info *bis)
int i;
struct ccsr_fman *reg;
- reg = (void *)CONFIG_SYS_FSL_FM1_ADDR;
+ reg = (void *)CFG_SYS_FSL_FM1_ADDR;
if (fm_init_common(0, reg))
return 0;
@@ -102,7 +102,7 @@ int fm_standard_init(struct bd_info *bis)
}
#if (CONFIG_SYS_NUM_FMAN == 2)
- reg = (void *)CONFIG_SYS_FSL_FM2_ADDR;
+ reg = (void *)CFG_SYS_FSL_FM2_ADDR;
if (fm_init_common(1, reg))
return 0;
@@ -247,7 +247,7 @@ int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset;
#ifndef CONFIG_SYS_FMAN_V3
u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS +
- CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET;
+ CFG_SYS_FSL_FM1_DTSEC1_OFFSET;
#endif
off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
diff --git a/drivers/net/fm/ls1043.c b/drivers/net/fm/ls1043.c
index cd8376a6150d..3db5c907a2ab 100644
--- a/drivers/net/fm/ls1043.c
+++ b/drivers/net/fm/ls1043.c
@@ -35,7 +35,7 @@ u32 port_to_devdisr[] = {
static int is_device_disabled(enum fm_port port)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
@@ -43,14 +43,14 @@ static int is_device_disabled(enum fm_port port)
void fman_disable_port(enum fm_port port)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
diff --git a/drivers/net/fm/ls1046.c b/drivers/net/fm/ls1046.c
index 876f48b14775..3b0ee98ddd35 100644
--- a/drivers/net/fm/ls1046.c
+++ b/drivers/net/fm/ls1046.c
@@ -35,7 +35,7 @@ u32 port_to_devdisr[] = {
static int is_device_disabled(enum fm_port port)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
@@ -43,14 +43,14 @@ static int is_device_disabled(enum fm_port port)
void fman_disable_port(enum fm_port port)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
diff --git a/drivers/net/ldpaa_eth/ls1088a.c b/drivers/net/ldpaa_eth/ls1088a.c
index 943113b20aa2..32bcb51725ac 100644
--- a/drivers/net/ldpaa_eth/ls1088a.c
+++ b/drivers/net/ldpaa_eth/ls1088a.c
@@ -25,7 +25,7 @@ u32 dpmac_to_devdisr[] = {
static int is_device_disabled(int dpmac_id)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 devdisr2 = in_le32(&gur->devdisr2);
return dpmac_to_devdisr[dpmac_id] & devdisr2;
@@ -33,14 +33,14 @@ static int is_device_disabled(int dpmac_id)
void wriop_dpmac_disable(int dpmac_id)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
}
void wriop_dpmac_enable(int dpmac_id)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
}
@@ -90,7 +90,7 @@ void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
#ifdef CONFIG_SYS_FSL_HAS_RGMII
void fsl_rgmii_init(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 ec;
#ifdef CONFIG_SYS_FSL_EC1
diff --git a/drivers/net/ldpaa_eth/ls2080a.c b/drivers/net/ldpaa_eth/ls2080a.c
index 62e1d6b86910..845a36bce875 100644
--- a/drivers/net/ldpaa_eth/ls2080a.c
+++ b/drivers/net/ldpaa_eth/ls2080a.c
@@ -37,7 +37,7 @@ u32 dpmac_to_devdisr[] = {
static int is_device_disabled(int dpmac_id)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 devdisr2 = in_le32(&gur->devdisr2);
return dpmac_to_devdisr[dpmac_id] & devdisr2;
@@ -45,14 +45,14 @@ static int is_device_disabled(int dpmac_id)
void wriop_dpmac_disable(int dpmac_id)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
}
void wriop_dpmac_enable(int dpmac_id)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
}
diff --git a/drivers/net/ldpaa_eth/lx2160a.c b/drivers/net/ldpaa_eth/lx2160a.c
index f0f8ee1d4de7..c2641a92d7ec 100644
--- a/drivers/net/ldpaa_eth/lx2160a.c
+++ b/drivers/net/ldpaa_eth/lx2160a.c
@@ -33,7 +33,7 @@ u32 dpmac_to_devdisr[] = {
static int is_device_disabled(int dpmac_id)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 devdisr2 = in_le32(&gur->devdisr2);
return dpmac_to_devdisr[dpmac_id] & devdisr2;
@@ -41,14 +41,14 @@ static int is_device_disabled(int dpmac_id)
void wriop_dpmac_disable(int dpmac_id)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
}
void wriop_dpmac_enable(int dpmac_id)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
}
@@ -84,7 +84,7 @@ phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
#ifdef CONFIG_SYS_FSL_HAS_RGMII
void fsl_rgmii_init(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 ec;
#ifdef CONFIG_SYS_FSL_EC1
diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
index d338b363d57c..ab532c5a420e 100644
--- a/drivers/net/pfe_eth/pfe_eth.c
+++ b/drivers/net/pfe_eth/pfe_eth.c
@@ -51,7 +51,7 @@ static inline void pfe_gemac_disable(void *gemac_base)
static inline void pfe_gemac_set_speed(void *gemac_base, u32 speed)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 ecr = readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED;
u32 rcr = readl(gemac_base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T;
u32 rgmii_pcr = in_be32(&scfg->rgmiipcr) &
diff --git a/drivers/net/pfe_eth/pfe_mdio.c b/drivers/net/pfe_eth/pfe_mdio.c
index ae5b6fc2800a..ff48726dbf55 100644
--- a/drivers/net/pfe_eth/pfe_mdio.c
+++ b/drivers/net/pfe_eth/pfe_mdio.c
@@ -213,7 +213,7 @@ int pfe_phy_configure(struct pfe_eth_dev *priv, int dev_id, int phy_id)
struct phy_device *phydev = NULL;
struct udevice *dev = priv->dev;
struct gemac_s *gem = priv->gem;
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
if (!gem->bus)
return -1;
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 59c38f905771..a8f8c31bef8f 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -463,7 +463,7 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie)
if (!fsl_pcie_link_up(pcie)) {
serdes_corenet_t *srds_regs;
- srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ srds_regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
val_32 = in_be32(&srds_regs->srdspccr0);
if ((val_32 >> 28) == 3) {
diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c
index a163300ab6b8..7180b5127a5b 100644
--- a/drivers/power/power_fsl.c
+++ b/drivers/power/power_fsl.c
@@ -47,7 +47,7 @@ int pmic_init(unsigned char bus)
p->hw.spi.prepare_tx = pmic_spi_prepare_tx;
#elif defined(CONFIG_POWER_I2C)
p->interface = PMIC_I2C;
- p->hw.i2c.addr = CONFIG_SYS_FSL_PMIC_I2C_ADDR;
+ p->hw.i2c.addr = CFG_SYS_FSL_PMIC_I2C_ADDR;
p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH;
#else
#error "You must select CONFIG_POWER_SPI or CONFIG_POWER_I2C"
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 2799ef374d26..fb1f683f9bd4 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -238,7 +238,7 @@ void u_qe_init(void)
if (src == BOOT_SOURCE_QSPI_NOR)
addr = (void *)(CONFIG_SYS_QE_FW_ADDR +
- CONFIG_SYS_FSL_QSPI_BASE);
+ CFG_SYS_FSL_QSPI_BASE);
if (src == BOOT_SOURCE_SD_MMC) {
int dev = CONFIG_SYS_MMC_ENV_DEV;
@@ -467,7 +467,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
const struct qe_header *hdr;
#ifdef CONFIG_DEEP_SLEEP
#ifdef CONFIG_ARCH_LS1021A
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
#else
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
@@ -607,7 +607,7 @@ int u_qe_upload_firmware(const struct qe_firmware *firmware)
const struct qe_header *hdr;
#ifdef CONFIG_DEEP_SLEEP
#ifdef CONFIG_ARCH_LS1021A
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
#else
ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
@@ -720,7 +720,7 @@ int u_qe_firmware_resume(const struct qe_firmware *firmware, qe_map_t *qe_immrr)
#ifdef CONFIG_PPC
ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#else
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
#endif
#endif
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 2529c9380dbb..ced01249285c 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -216,7 +216,7 @@
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC_PIN_MUX
-#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC83xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC83xx_ESDHC_ADDR
#endif
/*
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 03b823db0e18..addb306d57fc 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -392,7 +392,7 @@ extern unsigned long get_sdram_size(void);
#endif /* CONFIG_TSEC_ENET */
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/*
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index c2c03c82eb10..50cb6222d33a 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -308,7 +308,7 @@
#endif
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/*
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 2366b2abdca4..463fa6c714c6 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -365,7 +365,7 @@
* SDHC
*/
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/* Qman/Bman */
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 148c9c425d80..77e1d9f14132 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -346,7 +346,7 @@
*/
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/* Qman/Bman */
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 5e54a1fe66e5..d0cd15012070 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -422,7 +422,7 @@
* SDHC
*/
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/*
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 49d6eaf79c8e..dfaf0d095d01 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -379,7 +379,7 @@
* SDHC
*/
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/*
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 493c195aa607..9e40c572d6f2 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -382,7 +382,7 @@
*/
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h
index c9f876f5da7e..e2e491bdb0aa 100644
--- a/include/configs/apalis-imx8.h
+++ b/include/configs/apalis-imx8.h
@@ -9,7 +9,7 @@
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
@@ -61,7 +61,7 @@
/* Link Definitions */
/* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */
-#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 8f3389434757..192c9cf0c30c 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -22,8 +22,8 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 3
/* Network */
#define PHY_ANEG_TIMEOUT 15000 /* PHY needs longer aneg time */
diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h
index 8997c6a0ea90..1f2b3b58ca69 100644
--- a/include/configs/aristainetos2.h
+++ b/include/configs/aristainetos2.h
@@ -26,7 +26,7 @@
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0
@@ -412,7 +412,7 @@
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
/* DMA stuff, needed for GPMI/MXS NAND support */
diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h
index 2c0bf877e86b..c395384c8d38 100644
--- a/include/configs/cgtqmx8.h
+++ b/include/configs/cgtqmx8.h
@@ -20,7 +20,7 @@
/* Flat Device Tree Definitions */
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#define USDHC3_BASE_ADDR 0x5B030000
@@ -109,7 +109,7 @@
/* Link Definitions */
-#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h
index 1043eb75060f..cbf85341a64d 100644
--- a/include/configs/cl-som-imx7.h
+++ b/include/configs/cl-som-imx7.h
@@ -92,9 +92,9 @@
/* MMC Config*/
#ifdef CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
#endif
/* USB Configs */
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index e5e8c13090a8..874c0eb2175a 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -15,8 +15,8 @@
/* Machine config */
/* MMC */
-#define CONFIG_SYS_FSL_USDHC_NUM 3
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* RAM */
#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
index 2d29503a985d..f111abce3397 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -18,8 +18,8 @@
/* ENET1 */
/* MMC Config */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CFG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 1
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h
index 5d6449c7f74a..d641fbf47e75 100644
--- a/include/configs/colibri-imx8x.h
+++ b/include/configs/colibri-imx8x.h
@@ -10,7 +10,7 @@
#include <linux/sizes.h>
#include <linux/stringify.h>
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
@@ -94,7 +94,7 @@
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
/* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index d8b873662384..14fdf5b50e66 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -22,8 +22,8 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
/* USB Configs */
/* Host */
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index c95b732f8dcc..7380440ae7aa 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -14,11 +14,11 @@
#include "mx7_common.h"
/* MMC Config*/
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
-#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CFG_SYS_FSL_USDHC_NUM 1
#elif CONFIG_TARGET_COLIBRI_IMX7_EMMC
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
#endif
#define CONFIG_IPADDR 192.168.10.2
diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h
index 36052fe7d867..6079596caec0 100644
--- a/include/configs/dart_6ul.h
+++ b/include/configs/dart_6ul.h
@@ -15,9 +15,9 @@
/* NAND pin conflicts with usdhc2 */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CFG_SYS_FSL_USDHC_NUM 1
#else
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
#endif
#ifdef CONFIG_CMD_NET
@@ -35,7 +35,7 @@
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* I2C configs */
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index 2040deb2b877..54b2192b4a83 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -27,8 +27,8 @@
/* Miscellaneous configurable options */
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 3
/* UART */
#define CONFIG_MXC_UART_BASE UART1_BASE
diff --git a/include/configs/display5.h b/include/configs/display5.h
index c23a57ee7a2b..eb65f17cbe48 100644
--- a/include/configs/display5.h
+++ b/include/configs/display5.h
@@ -42,8 +42,8 @@
#define CONFIG_I2C_MULTI_BUS
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
#define PARTS_DEFAULT \
/* Linux partitions */ \
diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h
index 7fc3459ef295..affe20a10198 100644
--- a/include/configs/el6x_common.h
+++ b/include/configs/el6x_common.h
@@ -17,8 +17,8 @@
#endif
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
/* PMIC */
#define CONFIG_POWER_PFUZE100
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
index 7526d3b0f515..555239b8e813 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -22,7 +22,7 @@
#define CONFIG_MXC_USB_FLAGS 0
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
@@ -36,11 +36,11 @@
#if defined(CONFIG_ENV_IS_IN_MMC)
/* RiOTboard */
#define CONFIG_FDTFILE "imx6dl-riotboard.dtb"
-#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_USDHC_NUM 3
#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
/* MarSBoard */
#define CONFIG_FDTFILE "imx6q-marsboard.dtb"
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
#endif
/* Framebuffer */
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index ad00769bdeef..c46102fc3f3d 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -100,7 +100,7 @@
/* environment organization */
-#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_USDHC_NUM 3
/* Framebuffer */
#define CONFIG_HIDE_LOGO_VERSION
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 7300fcd90ba9..abfac3dc5e5f 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -22,7 +22,7 @@
/* NAND */
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
/*
* PCI express
diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h
index 619399366a23..a4dbf6daa6dd 100644
--- a/include/configs/imx6_logic.h
+++ b/include/configs/imx6_logic.h
@@ -18,8 +18,8 @@
#include "mx6_common.h"
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
/* Ethernet Configs */
diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h
index 201684ba802c..5025ad9d9f2e 100644
--- a/include/configs/imx6q-bosch-acc.h
+++ b/include/configs/imx6q-bosch-acc.h
@@ -94,17 +94,17 @@
#include "imx6_spl.h"
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
#ifdef CONFIG_SYS_BOOT_EMMC
/* Boot from eMMC */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 1
+#define CFG_SYS_FSL_ESDHC_ADDR 1
#else
/* Boot from SD-card */
-# define CONFIG_SYS_FSL_ESDHC_ADDR 0
+# define CFG_SYS_FSL_ESDHC_ADDR 0
#endif
diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h
index f0f800b8409b..caa6a11d4077 100644
--- a/include/configs/imx7-cm.h
+++ b/include/configs/imx7-cm.h
@@ -74,8 +74,8 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Config*/
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CFG_SYS_FSL_USDHC_NUM 2
/* USB Configs */
diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h
index 8046a13e8003..917d567d2eca 100644
--- a/include/configs/imx8mm-cl-iot-gate.h
+++ b/include/configs/imx8mm-cl-iot-gate.h
@@ -133,8 +133,8 @@
/* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_FEC_MXC_PHYADDR 0
diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h
index 363378b574c7..dd9f93f35c29 100644
--- a/include/configs/imx8mm_data_modul_edm_sbc.h
+++ b/include/configs/imx8mm_data_modul_edm_sbc.h
@@ -31,8 +31,8 @@
#define PHY_ANEG_TIMEOUT 20000
/* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_EXTRA_ENV_SETTINGS \
"altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \
diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h
index 66bc8eef8d96..9cdba70493b2 100644
--- a/include/configs/imx8mm_icore_mx8mm.h
+++ b/include/configs/imx8mm_icore_mx8mm.h
@@ -48,7 +48,7 @@
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
/* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif /* __IMX8MM_ICORE_MX8MM_H */
diff --git a/include/configs/imx8mn_bsh_smm_s2pro.h b/include/configs/imx8mn_bsh_smm_s2pro.h
index 37fda66f98e6..035e5c7bd90f 100644
--- a/include/configs/imx8mn_bsh_smm_s2pro.h
+++ b/include/configs/imx8mn_bsh_smm_s2pro.h
@@ -30,6 +30,6 @@
#define PHYS_SDRAM_SIZE SZ_512M
/* USDHC */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif /* __IMX8MN_BSH_SMM_S2PRO_H */
diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h
index a1a93e6bee57..a484d9136492 100644
--- a/include/configs/imx8mn_var_som.h
+++ b/include/configs/imx8mn_var_som.h
@@ -51,6 +51,6 @@
#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
/* USDHC */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif /* __IMX8MN_VAR_SOM_H */
diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h
index 124119edc98b..bf8782513644 100644
--- a/include/configs/imx8mp_dhcom_pdk2.h
+++ b/include/configs/imx8mp_dhcom_pdk2.h
@@ -25,8 +25,8 @@
#define FEC_QUIRK_ENET_MAC
/* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_EXTRA_ENV_SETTINGS \
"altbootcmd=run bootcmd ; reset\0" \
diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h
index 5caabf21a646..5be46090a145 100644
--- a/include/configs/imx8mp_rsb3720.h
+++ b/include/configs/imx8mp_rsb3720.h
@@ -150,8 +150,8 @@
#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#ifdef CONFIG_FSL_FSPI
#define FSL_FSPI_FLASH_SIZE SZ_32M
diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h
index 6aad04e9e97e..4b2107e40574 100644
--- a/include/configs/imx8mq_cm.h
+++ b/include/configs/imx8mq_cm.h
@@ -56,7 +56,7 @@
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index 8ecd3b7c2717..2d4c8d78c676 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -62,7 +62,7 @@
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif
diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h
index df5af640d45e..1905e538c5be 100644
--- a/include/configs/imx8mq_phanbell.h
+++ b/include/configs/imx8mq_phanbell.h
@@ -94,7 +94,7 @@
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif
diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h
index 308f17fd5959..67f19bc19220 100644
--- a/include/configs/imx8qm_rom7720.h
+++ b/include/configs/imx8qm_rom7720.h
@@ -11,7 +11,7 @@
#include <asm/arch/imx-regs.h>
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#define USDHC3_BASE_ADDR 0x5B030000
@@ -106,7 +106,7 @@
* USDHC3 is for SD on base board On DDR4 board, USDHC1 is mux for NAND,
* USDHC2 is for SD, USDHC3 is for SD on base board
*/
-#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h
index a9749a1bcaa2..b28146640863 100644
--- a/include/configs/imx93_evk.h
+++ b/include/configs/imx93_evk.h
@@ -131,7 +131,7 @@
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h
index f0586f7f721b..e36dc3f92f95 100644
--- a/include/configs/kontron-sl-mx6ul.h
+++ b/include/configs/kontron-sl-mx6ul.h
@@ -45,8 +45,8 @@
/* MMC Configs */
#ifdef CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CFG_SYS_FSL_USDHC_NUM 2
#endif
#define CONFIG_EXTRA_ENV_SETTINGS BOOTENV
diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h
index 5b461d290b70..6acd2f792534 100644
--- a/include/configs/kontron_pitx_imx8m.h
+++ b/include/configs/kontron_pitx_imx8m.h
@@ -70,7 +70,7 @@
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif
diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h
index de20f9b2e002..38860bfd5ca8 100644
--- a/include/configs/kontron_sl28.h
+++ b/include/configs/kontron_sl28.h
@@ -20,7 +20,7 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
@@ -32,7 +32,7 @@
/* generic timer */
/* early heap for SPL DM */
-#define CONFIG_MALLOC_F_ADDR CONFIG_SYS_FSL_OCRAM_BASE
+#define CONFIG_MALLOC_F_ADDR CFG_SYS_FSL_OCRAM_BASE
/* serial port */
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
diff --git a/include/configs/librem5.h b/include/configs/librem5.h
index a83363ec869a..dbd7d107dae9 100644
--- a/include/configs/librem5.h
+++ b/include/configs/librem5.h
@@ -25,7 +25,7 @@
#endif /* CONFIG_SPL_BUILD*/
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
#define CONFIG_USBD_HS
@@ -88,6 +88,6 @@
/* Monitor Command Prompt */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif
diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h
index a1fc056c305a..a784002158b0 100644
--- a/include/configs/liteboard.h
+++ b/include/configs/liteboard.h
@@ -20,7 +20,7 @@
/* MMC Configs */
#ifdef CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 87eb10db19fd..77f84e1c9eaa 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -11,12 +11,12 @@
#include <linux/sizes.h>
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
/*SPI device */
-#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
+#define CFG_SYS_FSL_QSPI_BASE 0x40000000
/* SATA */
diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h
index a0ff3b897904..1b417c72e704 100644
--- a/include/configs/ls1012afrwy.h
+++ b/include/configs/ls1012afrwy.h
@@ -17,7 +17,7 @@
#define SYS_SDRAM_SIZE_1024 0x40000000
/* ENV */
-#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
+#define CFG_SYS_FSL_QSPI_BASE 0x40000000
#undef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index 24422665e876..43dbeea1b3bd 100644
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.h
@@ -14,7 +14,7 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
@@ -57,7 +57,7 @@
"env exists secureboot && esbc_halt;"
#define OCRAM_NONSECURE_SIZE 0x00010000
-#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
+#define CFG_SYS_FSL_QSPI_BASE 0x20000000
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index c43eb232fb27..4468070d5a85 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -33,7 +33,7 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index e94ed26337c9..1eedbdef246d 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -33,7 +33,7 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h
index 582b1ee93cd0..48408f285834 100644
--- a/include/configs/ls1046afrwy.h
+++ b/include/configs/ls1046afrwy.h
@@ -73,7 +73,7 @@
/*
* Environment
*/
-#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
+#define CFG_SYS_FSL_QSPI_BASE 0x40000000
#undef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index f5f16bae2d60..769349336af9 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -104,7 +104,7 @@
/*
* Environment
*/
-#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
+#define CFG_SYS_FSL_QSPI_BASE 0x40000000
#define AQR105_IRQ_MASK 0x80000000
/* FMan */
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index bbe52824ccd9..846667c325ec 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -27,11 +27,11 @@
/* Link Definitions */
/* Link Definitions */
-#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
+#define CFG_SYS_FSL_QSPI_BASE 0x20000000
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
/*
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index b0f686084f48..9f5ca2c7a034 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -18,7 +18,7 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 59e54bf6f074..8b2b7479c11b 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -15,7 +15,7 @@
/* DDR */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index bf1560b23b95..f3259f7e5de2 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h
@@ -37,7 +37,7 @@
* MMC Driver
*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif
/*
diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h
index 17986a0e348a..69ca7c527534 100644
--- a/include/configs/mccmon6.h
+++ b/include/configs/mccmon6.h
@@ -22,8 +22,8 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configuration */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
/* NOR 16-bit mode */
#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index fbc9a0416938..95afb350ec34 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -34,7 +34,7 @@
/*
* MMC Configs
* */
-#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
/* USB Configs */
#define CONFIG_MXC_USB_PORT 1
diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h
index d58d1534a3bd..778356397202 100644
--- a/include/configs/mx53cx9020.h
+++ b/include/configs/mx53cx9020.h
@@ -17,7 +17,7 @@
#define CONFIG_MXC_UART_BASE UART2_BASE
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
/* bootz: zImage/initrd.img support */
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 60ec34cf8e06..3c9b2ad58ee4 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -14,7 +14,7 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
/* USB Configs */
#define CONFIG_MXC_USB_PORT 1
@@ -25,7 +25,7 @@
#define CONFIG_POWER_FSL
#define CONFIG_POWER_FSL_MC13892
#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
-#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
+#define CFG_SYS_FSL_PMIC_I2C_ADDR 0x8
/* Command definition */
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index cffbb64bcd53..bc90b9563ade 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -14,7 +14,7 @@
#include "imx6_spl.h"
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* Framebuffer */
#define CONFIG_IMX_HDMI
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index bfcab1bed5b8..bc9fab12909a 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -13,7 +13,7 @@
#include "mx6_common.h"
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#ifdef CONFIG_SUPPORT_EMMC_BOOT
#define EMMC_ENV \
diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h
index 7e54bb2312bc..61570b7af534 100644
--- a/include/configs/mx6sabreauto.h
+++ b/include/configs/mx6sabreauto.h
@@ -33,7 +33,7 @@
#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
#endif
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
/* NAND stuff */
#define CONFIG_SYS_NAND_BASE 0x40000000
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index 16f8858abb8f..49cd1512dc58 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -21,7 +21,7 @@
/* Falcon Mode - MMC support: args at 1MB kernel at 2MB */
-#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_USDHC_NUM 3
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 9f890938f982..26b97bd3f2e4 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -17,7 +17,7 @@
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
@@ -98,6 +98,6 @@
#define CONFIG_MXC_USB_FLAGS 0
#endif
-#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_USDHC_NUM 3
#endif /* __CONFIG_H */
diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h
index e9ccb99d3cec..44a5eeff1984 100644
--- a/include/configs/mx6sllevk.h
+++ b/include/configs/mx6sllevk.h
@@ -89,8 +89,8 @@
/* Environment organization */
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
-#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CFG_SYS_FSL_USDHC_NUM 3
#define CONFIG_IOMUX_LPSR
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index 407b64383ee6..0d9764e3b4c1 100644
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h
@@ -83,7 +83,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Configuration */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
/* NAND stuff */
#define CONFIG_SYS_NAND_BASE 0x40000000
@@ -100,6 +100,6 @@
#define CONFIG_MXC_USB_FLAGS 0
#endif
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
#endif /* __CONFIG_H */
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 570e2ce687ac..83779f09bfc6 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -115,7 +115,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Configuration */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
/* Network */
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index ab56ea0205da..d0e3d3f02849 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -22,13 +22,13 @@
/* MMC Configs */
#ifdef CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* NAND pin conflicts with usdhc2 */
#ifdef CONFIG_NAND_MXS
-#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CFG_SYS_FSL_USDHC_NUM 1
#else
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
#endif
#endif
diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h
index 00cc547b900c..604923ec2b77 100644
--- a/include/configs/mx6ullevk.h
+++ b/include/configs/mx6ullevk.h
@@ -20,8 +20,8 @@
/* MMC Configs */
#ifdef CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_USDHC_NUM 2
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h
index bb68ddbd39da..a777305ec76e 100644
--- a/include/configs/mys_6ulx.h
+++ b/include/configs/mys_6ulx.h
@@ -13,13 +13,13 @@
/* SPL options */
#include "imx6_spl.h"
-#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CFG_SYS_FSL_USDHC_NUM 1
/* Console configs */
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 26e6de2d2c8d..af6fa6a12681 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -16,8 +16,8 @@
#define CONFIG_MXC_UART_BASE UART2_BASE
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 6
diff --git a/include/configs/novena.h b/include/configs/novena.h
index 1696aa28520f..f2a04ca61854 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -43,8 +43,8 @@
/* I2C EEPROM */
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
/* PCI express */
#ifdef CONFIG_CMD_PCI
diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h
index 8ff26feb741d..ccc203f5f24d 100644
--- a/include/configs/npi_imx6ull.h
+++ b/include/configs/npi_imx6ull.h
@@ -13,13 +13,13 @@
/* SPL options */
#include "imx6_spl.h"
-#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CFG_SYS_FSL_USDHC_NUM 1
/* Console configs */
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
#define CONFIG_NETMASK 255.255.255.0
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index db4aa81bbbc4..75d35d96c6b9 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -417,7 +417,7 @@
*/
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/*
diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h
index 5b38a94aa5d1..dea87122ebc6 100644
--- a/include/configs/pcl063.h
+++ b/include/configs/pcl063.h
@@ -22,14 +22,14 @@
* Tweak the SPL text base address to avoid this.
*/
-#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CFG_SYS_FSL_USDHC_NUM 1
/* Console configs */
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
/* Miscellaneous configurable options */
diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h
index 688d161964a4..2bdae8afa8c1 100644
--- a/include/configs/pcl063_ull.h
+++ b/include/configs/pcl063_ull.h
@@ -16,7 +16,7 @@
/* SPL options */
#include "imx6_spl.h"
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
/* Environment settings */
@@ -29,7 +29,7 @@
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* I2C configs */
diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h
index dcbcd8d24495..687133b9bdda 100644
--- a/include/configs/pico-imx6.h
+++ b/include/configs/pico-imx6.h
@@ -21,7 +21,7 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configuration */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index 2ac48c40c96e..8402efaf5bbe 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -27,7 +27,7 @@
#define CONFIG_MXC_UART_BASE UART6_BASE_ADDR
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h
index 7fbf2c3f55fb..159bf4c68ca5 100644
--- a/include/configs/pico-imx7d.h
+++ b/include/configs/pico-imx7d.h
@@ -21,7 +21,7 @@
#define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR
/* MMC Config */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_DFU_ENV_SETTINGS \
"dfu_alt_info=" \
@@ -113,7 +113,7 @@
/* Environment starts at 768k = 768 * 1024 = 786432 */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h
index 1ee1edbdfffa..17af19d49dc1 100644
--- a/include/configs/pico-imx8mq.h
+++ b/include/configs/pico-imx8mq.h
@@ -73,7 +73,7 @@
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif
diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 681c831747ba..faa13c65216f 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -15,7 +15,7 @@
#define PHYS_SDRAM_SIZE SZ_512M
/* MMC Config*/
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_EXTRA_ENV_SETTINGS \
"image=zImage\0" \
diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h
index eeee587bafd5..49672dfe7c3f 100644
--- a/include/configs/somlabs_visionsom_6ull.h
+++ b/include/configs/somlabs_visionsom_6ull.h
@@ -19,9 +19,9 @@
/* MMC Configs */
#ifdef CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CFG_SYS_FSL_USDHC_NUM 1
#endif /* CONFIG_FSL_USDHC */
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
index 9498dbeadf41..2c5891589525 100644
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h
@@ -44,7 +44,7 @@
#endif
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/udoo.h b/include/configs/udoo.h
index 03e5c04af6ee..8af5151c503d 100644
--- a/include/configs/udoo.h
+++ b/include/configs/udoo.h
@@ -15,7 +15,7 @@
#define CONFIG_MXC_UART_BASE UART2_BASE
/* MMC Configuration */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttymxc1,115200\0" \
diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h
index e30b6cc82d8b..093e2e8dae7c 100644
--- a/include/configs/udoo_neo.h
+++ b/include/configs/udoo_neo.h
@@ -15,7 +15,7 @@
#include "imx6_spl.h"
/* MMC Configuration */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* Command definition */
#define CONFIG_MXC_UART_BASE UART1_BASE
diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h
index 08a6f5fbccdc..c381934f31a9 100644
--- a/include/configs/usbarmory.h
+++ b/include/configs/usbarmory.h
@@ -20,7 +20,7 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
/* SD/MMC */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
/* USB */
#define CONFIG_MXC_USB_PORT 1
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index dde6d130caa6..7e3d3473b442 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -19,7 +19,7 @@
/* Dynamic MTD partition support */
#endif
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_FEC_MXC_PHYADDR 0
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h
index 6eb022f26c5f..a4484fd3f8ca 100644
--- a/include/configs/vining_2000.h
+++ b/include/configs/vining_2000.h
@@ -32,7 +32,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Configuration */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
/* PMIC */
#define CONFIG_POWER_PFUZE100
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 899b8ca470e2..91c1f4b3b514 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -15,8 +15,8 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configuration */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index a9cc85953576..a4b12dc55ed0 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -14,7 +14,7 @@
#define PHYS_SDRAM_SIZE SZ_512M
/* MMC Config*/
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
#define CONFIG_DFU_ENV_SETTINGS \
"dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \
@@ -90,7 +90,7 @@
/* environment organization */
-#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CFG_SYS_FSL_USDHC_NUM 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/xpress.h b/include/configs/xpress.h
index 0e43b373649a..fc8ec3204b1b 100644
--- a/include/configs/xpress.h
+++ b/include/configs/xpress.h
@@ -16,7 +16,7 @@
#define CONFIG_MXC_UART_BASE MX6UL_UART7_BASE_ADDR
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* Miscellaneous configurable options */
diff --git a/include/fm_eth.h b/include/fm_eth.h
index bf9570679d2e..7475b5150738 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -51,18 +51,18 @@ enum fm_eth_type {
*/
#ifdef CONFIG_SYS_FMAN_V3
#ifdef CONFIG_TARGET_LS1046AFRWY
-#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
+#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfd000)
#else
-#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
+#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfc000)
#endif
-#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
+#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfd000)
#if (CONFIG_SYS_NUM_FMAN == 2)
-#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
-#define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
+#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfc000)
+#define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfd000)
#endif
#else
-#define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
-#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
+#define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xe1120)
+#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xf1000)
#endif
#define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
@@ -84,7 +84,7 @@ enum fm_eth_type {
.port = FM##idx##_DTSEC##n, \
.rx_port_id = RX_PORT_1G_BASE + n - 1, \
.tx_port_id = TX_PORT_1G_BASE + n - 1, \
- .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+ .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, memac[n-1]),\
}
@@ -98,7 +98,7 @@ enum fm_eth_type {
.port = FM##idx##_10GEC##n, \
.rx_port_id = RX_PORT_10G_BASE2 + n - 1, \
.tx_port_id = TX_PORT_10G_BASE2 + n - 1, \
- .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+ .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, memac[n-1]),\
}
#else
@@ -112,7 +112,7 @@ enum fm_eth_type {
.port = FM##idx##_10GEC##n, \
.rx_port_id = RX_PORT_10G_BASE + n - 1, \
.tx_port_id = TX_PORT_10G_BASE + n - 1, \
- .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+ .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, memac[n-1+8]),\
}
#else
@@ -125,7 +125,7 @@ enum fm_eth_type {
.port = FM##idx##_10GEC##n, \
.rx_port_id = RX_PORT_10G_BASE + n - 1, \
.tx_port_id = TX_PORT_10G_BASE + n - 1, \
- .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+ .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, memac[n-1+8]),\
}
#endif
@@ -141,7 +141,7 @@ enum fm_eth_type {
.port = FM##idx##_10GEC##n, \
.rx_port_id = RX_PORT_10G_BASE2 + n - 3, \
.tx_port_id = TX_PORT_10G_BASE2 + n - 3, \
- .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+ .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, memac[n-1-2]),\
}
#endif
@@ -156,7 +156,7 @@ enum fm_eth_type {
.port = FM##idx##_DTSEC##n, \
.rx_port_id = RX_PORT_1G_BASE + n - 1, \
.tx_port_id = TX_PORT_1G_BASE + n - 1, \
- .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+ .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, mac_1g[n-1]),\
}
@@ -169,7 +169,7 @@ enum fm_eth_type {
.port = FM##idx##_10GEC##n, \
.rx_port_id = RX_PORT_10G_BASE + n - 1, \
.tx_port_id = TX_PORT_10G_BASE + n - 1, \
- .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+ .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, mac_10g[n-1]),\
}
#endif
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index d57c4ca820c8..d8861d1d0b76 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -272,7 +272,7 @@ struct sg_entry {
#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
/* Job Ring Base Address */
-#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
+#define JR_BASE_ADDR(x) (CFG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
/* Secure Memory Offset varies accross versions */
#define SM_V1_OFFSET 0x0f4
#define SM_V2_OFFSET 0xa00
@@ -287,7 +287,7 @@ struct sg_entry {
/* JR Allocation Error */
#define SMCSJR_AERR (3 << 12)
/* Secure memory partition 0 page 0 owner register */
-#define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC)
+#define CAAM_SMPO_0 (CFG_SYS_FSL_SEC_ADDR + 0x1FBC)
/* Secure memory command register */
#define CAAM_SMCJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v))
/* Secure memory command status register */
--
2.25.1
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