[PATCH v2 22/32] clk: mediatek: add CLK_BYPASS_XTAL flag to allow bypassing searching clock parent of xtal clock

[Daniel Golle]

On Wed, Aug 31, 2022 at 07:04:59PM +0800, Weijie Gao wrote:
> The mtk clock framework in u-boot uses array index for searching clock
> parent (kernel uses strings for search), so we need to specify a special
> clock with ID=0 for CLK_XTAL in u-boot.
> 
> In the mt7622/mt7629 clock tree, the clocks with ID=0 never call
> mtk_topckgen_get_mux_rate, adn return xtal clock directly. This what we
> expected.
> 
> However for newer chips, they may have some clocks with ID=0 not
> representing the xtal clock and still needs mtk_topckgen_get_mux_rate be
> called. Current logic will make entire clock driver not working.
> 
> This patch adds a flag to indicate that whether a clock driver needs clocks
> with ID=0 to call mtk_topckgen_get_mux_rate.

Tested on Bananapi BPi-R3 (MT7986A).

Tested-by: Daniel Golle <daniel at makrotopia.org>

> 
> Reviewed-by: Simon Glass <sjg at chromium.org>
> Signed-off-by: Weijie Gao <weijie.gao at mediatek.com>
> ---
> v2 changes:
>   Add comment for flags
>   Fix the if condition of CLK_BYPASS_XTAL
> ---
>  drivers/clk/mediatek/clk-mtk.c | 4 +++-
>  drivers/clk/mediatek/clk-mtk.h | 6 ++++++
>  2 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
> index d43b8a0648..7d145f4975 100644
> --- a/drivers/clk/mediatek/clk-mtk.c
> +++ b/drivers/clk/mediatek/clk-mtk.c
> @@ -319,7 +319,9 @@ static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off)
>  	index &= mux->mux_mask << mux->mux_shift;
>  	index = index >> mux->mux_shift;
>  
> -	if (mux->parent[index])
> +	if (mux->parent[index] > 0 ||
> +	    (mux->parent[index] == CLK_XTAL &&
> +	     priv->tree->flags & CLK_BYPASS_XTAL))
>  		return mtk_clk_find_parent_rate(clk, mux->parent[index],
>  						NULL);
>  
> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> index 95a23d14a8..e0c5550c80 100644
> --- a/drivers/clk/mediatek/clk-mtk.h
> +++ b/drivers/clk/mediatek/clk-mtk.h
> @@ -11,6 +11,11 @@
>  #define CLK_XTAL			0
>  #define MHZ				(1000 * 1000)
>  
> +/* flags in struct mtk_clk_tree */
> +
> +/* clk id == 0 doesn't mean it's xtal clk */
> +#define CLK_BYPASS_XTAL			BIT(0)
> +
>  #define HAVE_RST_BAR			BIT(0)
>  #define CLK_DOMAIN_SCPSYS		BIT(0)
>  #define CLK_MUX_SETCLR_UPD		BIT(1)
> @@ -197,6 +202,7 @@ struct mtk_clk_tree {
>  	const struct mtk_fixed_clk *fclks;
>  	const struct mtk_fixed_factor *fdivs;
>  	const struct mtk_composite *muxes;
> +	u32 flags;
>  };
>  
>  struct mtk_clk_priv {
> -- 
> 2.17.1
>