[PATCH v2 25/32] clk: mediatek: add CLK_XTAL support for clock driver

[Daniel Golle]

On Wed, Aug 31, 2022 at 07:05:11PM +0800, Weijie Gao wrote:
> This adds the CLK_XTAL macro/flag to allow modeling clocks which are
> directly connected to the xtal clock.

Tested on Bananapi BPi-R3 (MT7986A).

Tested-by: Daniel Golle <daniel at makrotopia.org>

> 
> Signed-off-by: Weijie Gao <weijie.gao at mediatek.com>
> ---
> v2 changes:
>   Fix incorrect fallback in mtk_infrasys_get_factor_rate
>   Fix commit description
> ---
>  drivers/clk/mediatek/clk-mtk.c | 4 ++++
>  drivers/clk/mediatek/clk-mtk.h | 3 ++-
>  2 files changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
> index 207a4c6b11..4303300d3a 100644
> --- a/drivers/clk/mediatek/clk-mtk.c
> +++ b/drivers/clk/mediatek/clk-mtk.c
> @@ -296,6 +296,7 @@ static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)
>  		rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
>  		break;
>  
> +	case CLK_PARENT_XTAL:
>  	default:
>  		rate = priv->tree->xtal_rate;
>  	}
> @@ -314,6 +315,9 @@ static ulong mtk_infrasys_get_factor_rate(struct clk *clk, u32 off)
>  		rate = mtk_clk_find_parent_rate(clk, fdiv->parent,
>  						priv->parent);
>  		break;
> +	case CLK_PARENT_XTAL:
> +		rate = priv->tree->xtal_rate;
> +		break;
>  	default:
>  		rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
>  	}
> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> index e7c61ae483..48ce16484e 100644
> --- a/drivers/clk/mediatek/clk-mtk.h
> +++ b/drivers/clk/mediatek/clk-mtk.h
> @@ -29,7 +29,8 @@
>  #define CLK_PARENT_APMIXED		BIT(4)
>  #define CLK_PARENT_TOPCKGEN		BIT(5)
>  #define CLK_PARENT_INFRASYS		BIT(6)
> -#define CLK_PARENT_MASK			GENMASK(6, 4)
> +#define CLK_PARENT_XTAL			BIT(7)
> +#define CLK_PARENT_MASK			GENMASK(7, 4)
>  
>  #define ETHSYS_HIFSYS_RST_CTRL_OFS	0x34
>  
> -- 
> 2.17.1
>