[PATCH] arm: Enable cache-pl310 driver build for both SPL and proper U-Boot

[Jit Loon Lim]

From: Tien Fong Chee <tien.fong.chee at intel.com>

Moved CONFIG_SYS_L2_PL310 to the location where the build on the
cache-pl310 can be taken in both SPL and proper U-Boot. This driver is
required for SoCFPGA when temporarily turning on the cache for better
performance in initializing whole DDR to zero.

Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim at intel.com>
---
 arch/arm/lib/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index c603fe61bc..575042e6df 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -43,6 +43,7 @@ ifdef CONFIG_ARM64
 obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset-arm64.o
 obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy-arm64.o
 else
+obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
 obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o
 obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
 endif
-- 
2.26.2