[PATCH v1] arm: dts: rockchip: rk3128: fix DT node names
Kever Yang
kever.yang at rock-chips.com
Fri Sep 9 11:51:12 CEST 2022
Hi Johan,
If you would like to clean up and sync the dts with kernel for
rk3128, could you please group them in one patch set?
Or else it's very easy to lead to conflict.
Thanks,
- Kever
On 2022/9/5 05:37, Johan Jonker wrote:
> The rk3128 DT node names should be generic.
> Rename them to the pattern defined in the DT bindings.
>
> Signed-off-by: Johan Jonker <jbx6244 at gmail.com>
> ---
> arch/arm/dts/rk3128-evb.dts | 5 +++
> arch/arm/dts/rk3128.dtsi | 62 +++++++++++++++++--------------------
> 2 files changed, 33 insertions(+), 34 deletions(-)
>
> diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts
> index e7d8f7c9..93291d78 100644
> --- a/arch/arm/dts/rk3128-evb.dts
> +++ b/arch/arm/dts/rk3128-evb.dts
> @@ -15,6 +15,11 @@
> stdout-path = &uart2;
> };
>
> + memory at 60000000 {
> + device_type = "memory";
> + reg = <0x60000000 0x40000000>;
> + };
> +
> vcc5v0_otg: vcc5v0-otg-drv {
> compatible = "regulator-fixed";
> regulator-name = "vcc5v0_otg";
> diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi
> index 589818da..f66efde3 100644
> --- a/arch/arm/dts/rk3128.dtsi
> +++ b/arch/arm/dts/rk3128.dtsi
> @@ -8,7 +8,6 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/pinctrl/rockchip.h>
> #include <dt-bindings/clock/rk3128-cru.h>
> -#include "skeleton.dtsi"
>
> / {
> compatible = "rockchip,rk3128";
> @@ -34,11 +33,6 @@
> mmc1 = &sdmmc;
> };
>
> - memory {
> - device_type = "memory";
> - reg = <0x60000000 0x40000000>;
> - };
> -
> arm-pmu {
> compatible = "arm,cortex-a7-pmu";
> interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> @@ -52,10 +46,10 @@
> #size-cells = <0>;
> enable-method = "rockchip,rk3128-smp";
>
> - cpu0:cpu at 0x000 {
> + cpu0: cpu at 0 {
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> - reg = <0x000>;
> + reg = <0x0>;
> operating-points = <
> /* KHz uV */
> 816000 1000000
> @@ -65,22 +59,22 @@
> clocks = <&cru ARMCLK>;
> };
>
> - cpu1:cpu at 0x001 {
> + cpu1: cpu at 1 {
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> - reg = <0x001>;
> + reg = <0x1>;
> };
>
> - cpu2:cpu at 0x002 {
> + cpu2: cpu at 2 {
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> - reg = <0x002>;
> + reg = <0x2>;
> };
>
> - cpu3:cpu at 0x003 {
> + cpu3: cpu at 3 {
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> - reg = <0x003>;
> + reg = <0x3>;
> };
> };
>
> @@ -165,7 +159,7 @@
> interrupt-parent = <&gic>;
> ranges;
>
> - pdma: pdma at 20078000 {
> + pdma: dma-controller at 20078000 {
> compatible = "arm,pl330", "arm,primecell";
> reg = <0x20078000 0x4000>;
> arm,pl330-broken-no-flushp;//2
> @@ -207,7 +201,7 @@
> rockchip,broadcast = <1>;
> };
>
> - watchdog: wdt at 2004c000 {
> + watchdog: watchdog at 2004c000 {
> compatible = "rockchip,watch dog";
> reg = <0x2004c000 0x100>;
> clock-names = "pclk_wdt";
> @@ -224,7 +218,7 @@
> #reset-cells = <1>;
> };
>
> - nandc: nandc at 10500000 {
> + nandc: nand-controller at 10500000 {
> compatible = "rockchip,rk-nandc";
> reg = <0x10500000 0x4000>;
> interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> @@ -247,7 +241,7 @@
> assigned-clock-rates = <594000000>;
> };
>
> - uart0: serial0 at 20060000 {
> + uart0: serial at 20060000 {
> compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
> reg = <0x20060000 0x100>;
> interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> @@ -262,7 +256,7 @@
> #dma-cells = <2>;
> };
>
> - uart1: serial1 at 20064000 {
> + uart1: serial at 20064000 {
> compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
> reg = <0x20064000 0x100>;
> interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> @@ -277,7 +271,7 @@
> #dma-cells = <2>;
> };
>
> - uart2: serial2 at 20068000 {
> + uart2: serial at 20068000 {
> compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
> reg = <0x20068000 0x100>;
> interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> @@ -304,7 +298,7 @@
> status = "disabled";
> };
>
> - pwm0: pwm0 at 20050000 {
> + pwm0: pwm at 20050000 {
> compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
> reg = <0x20050000 0x10>;
> #pwm-cells = <3>;
> @@ -314,7 +308,7 @@
> clock-names = "pwm";
> };
>
> - pwm1: pwm1 at 20050010 {
> + pwm1: pwm at 20050010 {
> compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
> reg = <0x20050010 0x10>;
> #pwm-cells = <3>;
> @@ -324,7 +318,7 @@
> clock-names = "pwm";
> };
>
> - pwm2: pwm2 at 20050020 {
> + pwm2: pwm at 20050020 {
> compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
> reg = <0x20050020 0x10>;
> #pwm-cells = <3>;
> @@ -334,7 +328,7 @@
> clock-names = "pwm";
> };
>
> - pwm3: pwm3 at 20050030 {
> + pwm3: pwm at 20050030 {
> compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
> reg = <0x20050030 0x10>;
> #pwm-cells = <3>;
> @@ -430,7 +424,7 @@
> status = "disabled";
> };
>
> - sdmmc: dwmmc at 10214000 {
> + sdmmc: mmc at 10214000 {
> compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
> reg = <0x10214000 0x4000>;
> interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> @@ -444,7 +438,7 @@
> status = "disabled";
> };
>
> - emmc: dwmmc at 1021c000 {
> + emmc: mmc at 1021c000 {
> compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
> reg = <0x1021c000 0x4000>;
> interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> @@ -462,7 +456,7 @@
> status = "disabled";
> };
>
> - i2c0: i2c0 at 20072000 {
> + i2c0: i2c at 20072000 {
> compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
> reg = <20072000 0x1000>;
> interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> @@ -474,7 +468,7 @@
> pinctrl-0 = <&i2c0_xfer>;
> };
>
> - i2c1: i2c1 at 20056000 {
> + i2c1: i2c at 20056000 {
> compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
> reg = <0x20056000 0x1000>;
> interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> @@ -486,7 +480,7 @@
> pinctrl-0 = <&i2c1_xfer>;
> };
>
> - i2c2: i2c2 at 2005a000 {
> + i2c2: i2c at 2005a000 {
> compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
> reg = <0x2005a000 0x1000>;
> interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> @@ -498,7 +492,7 @@
> pinctrl-0 = <&i2c2_xfer>;
> };
>
> - i2c3: i2c3 at 2005e000 {
> + i2c3: i2c at 2005e000 {
> compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
> reg = <0x2005e000 0x1000>;
> interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> @@ -544,7 +538,7 @@
> #size-cells = <1>;
> ranges;
>
> - gpio0: gpio0 at 2007c000 {
> + gpio0: gpio at 2007c000 {
> compatible = "rockchip,gpio-bank";
> reg = <0x2007c000 0x100>;
> interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> @@ -555,7 +549,7 @@
> #interrupt-cells = <2>;
> };
>
> - gpio1: gpio1 at 20080000 {
> + gpio1: gpio at 20080000 {
> compatible = "rockchip,gpio-bank";
> reg = <0x20080000 0x100>;
> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> @@ -566,7 +560,7 @@
> #interrupt-cells = <2>;
> };
>
> - gpio2: gpio2 at 20084000 {
> + gpio2: gpio at 20084000 {
> compatible = "rockchip,gpio-bank";
> reg = <0x20084000 0x100>;
> interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> @@ -577,7 +571,7 @@
> #interrupt-cells = <2>;
> };
>
> - gpio3: gpio2 at 20088000 {
> + gpio3: gpio at 20088000 {
> compatible = "rockchip,gpio-bank";
> reg = <0x20088000 0x100>;
> interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
More information about the U-Boot
mailing list