[PATCH 8/9] ddr: fsl: Fix re-align of verbose DRAM information for non-SPL builds

[Tom Rini]

On Fri, Sep 09, 2022 at 01:39:25PM -0600, Simon Glass wrote:
> Hi Tom,
> 
> On Fri, 9 Sept 2022 at 13:08, Tom Rini <trini at konsulko.com> wrote:
> >
> > On Fri, Sep 09, 2022 at 12:21:11PM -0600, Simon Glass wrote:
> > > Hi,
> > >
> > > On Fri, 9 Sept 2022 at 09:34, Pali Rohár <pali at kernel.org> wrote:
> > > >
> > > > During init_dram() is called also compute_lowest_common_dimm_parameters()
> > > > function which prints multi-line detailed output. So print also re-aligning
> > > > filler after "Detected ?DIMM" line to have "DRAM:  " output aligned.
> > > >
> > > > Signed-off-by: Pali Rohár <pali at kernel.org>
> > > > ---
> > > >  drivers/ddr/fsl/lc_common_dimm_params.c | 3 +++
> > > >  1 file changed, 3 insertions(+)
> > >
> > > At some point could this move to drivers/ram ?
> >
> > Depends on if we're keeping / making drivers/ram mean uses uclass and
> > drivers/ddr does not, I think.
> 
> Yes, except for Altera:
> 
> $ git grep UCLASS_RAM drivers/ddr
> drivers/ddr/altera/sdram_gen5.c:    .id = UCLASS_RAM,
> drivers/ddr/altera/sdram_soc64.c:   .id = UCLASS_RAM,

Then we should move those over to drivers/ram/altera/ and leave the rest
as-is. And of course, totally outside the scope of this series.

-- 
Tom
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