[PATCH] arch: arm: mach-socfpga: HSD #1707095796: Remove MPFE Firewall for SMMU

[Jit Loon Lim]

From: Thor Thayer <thor.thayer at linux.intel.com>

Remove firewall on MPFE so that SMMU can setup/walk tables in
the DDR.

Signed-off-by: Thor Thayer <thor.thayer at linux.intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim at intel.com>
---
 arch/arm/mach-socfpga/firewall.c                     | 6 ++++++
 arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 1 +
 arch/arm/mach-socfpga/include/mach/firewall.h        | 1 +
 3 files changed, 8 insertions(+)

diff --git a/arch/arm/mach-socfpga/firewall.c b/arch/arm/mach-socfpga/firewall.c
index 69229dc651..bbfcdbd9ae 100644
--- a/arch/arm/mach-socfpga/firewall.c
+++ b/arch/arm/mach-socfpga/firewall.c
@@ -104,4 +104,10 @@ void firewall_setup(void)
 	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA);
 	writel(SYSMGR_DMAPERIPH_ALL_NS,
 	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA_PERIPH);
+
+#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+	/* Disable the MPFE Firewall for SMMU */
+	writel(FIREWALL_MPFE_SCR_DISABLE_ALL, SOCFPGA_FW_MPFE_SCR_ADDRESS);
+#endif
+
 }
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
index 3f899fcfa3..45c6458597 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
@@ -10,6 +10,7 @@
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xf8000400
 #define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xf8010000
 #define SOCFPGA_SDR_ADDRESS			0xf8011000
+#define SOCFPGA_FW_MPFE_SCR_ADDRESS		0xf8020000
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \
 	IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
 #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS		0xf8020200
diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h
index 5cb7f23f8f..885c04c27f 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -75,6 +75,7 @@ struct socfpga_firwall_l4_sys {
 };
 
 #define FIREWALL_L4_DISABLE_ALL		(BIT(0) | BIT(24) | BIT(16))
+#define FIREWALL_MPFE_SCR_DISABLE_ALL	(BIT(0) | BIT(8) | BIT(16))
 #define FIREWALL_BRIDGE_DISABLE_ALL	(~0)
 
 /* Cache coherency unit (CCU) registers */
-- 
2.26.2