[PATCH] arch: arm: mach-socfpga: HSD #1707102234: Agilex: Disable MPFE HMC Adapter Firewall

[Jit Loon Lim]

From: Thor Thayer <thor.thayer at linux.intel.com>

Disable the MPFE HMC Adapter Firewall for the MPU because
the Linux SDRAM ECC needs to access that register.
Also cleanup the HMC Firewall added for SMMU.

Signed-off-by: Thor Thayer <thor.thayer at linux.intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim at intel.com>
---
 arch/arm/mach-socfpga/firewall.c              | 10 ++++++++++
 arch/arm/mach-socfpga/include/mach/firewall.h |  5 +++++
 2 files changed, 15 insertions(+)

diff --git a/arch/arm/mach-socfpga/firewall.c b/arch/arm/mach-socfpga/firewall.c
index 69229dc651..c6c41b2134 100644
--- a/arch/arm/mach-socfpga/firewall.c
+++ b/arch/arm/mach-socfpga/firewall.c
@@ -104,4 +104,14 @@ void firewall_setup(void)
 	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA);
 	writel(SYSMGR_DMAPERIPH_ALL_NS,
 	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA_PERIPH);
+
+#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+	/* Disable the MPFE Firewall for SMMU */
+	writel(FIREWALL_MPFE_SCR_DISABLE_ALL, SOCFPGA_FW_MPFE_SCR_ADDRESS +
+					      FW_MPFE_SCR_HMC);
+	/* Disable MPFE Firewall for HMC adapter (ECC) */
+	writel(FIREWALL_MPFE_SCR_DISABLE_MPU, SOCFPGA_FW_MPFE_SCR_ADDRESS +
+					      FW_MPFE_SCR_HMC_ADAPTOR);
+#endif
+
 }
diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h
index 5cb7f23f8f..e45acb6501 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -75,6 +75,7 @@ struct socfpga_firwall_l4_sys {
 };
 
 #define FIREWALL_L4_DISABLE_ALL		(BIT(0) | BIT(24) | BIT(16))
+#define FIREWALL_MPFE_SCR_DISABLE_MPU	BIT(0)
 #define FIREWALL_BRIDGE_DISABLE_ALL	(~0)
 
 /* Cache coherency unit (CCU) registers */
@@ -126,6 +127,10 @@ struct socfpga_firwall_l4_sys {
 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT	0x9c
 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD	0xff
 
+/* Firewall MPFE SCR Registers */
+#define FW_MPFE_SCR_HMC					0x00
+#define FW_MPFE_SCR_HMC_ADAPTOR				0x04
+
 #define MPUREGION0_ENABLE				BIT(0)
 #define NONMPUREGION0_ENABLE				BIT(8)
 
-- 
2.26.2