[PATCH 0/2] Add riscv semihosting support in u-boot

[Kautuk Consul]

Hi Sean,

Will address your comment in v2 by moving the ARM and RISCV  code to generic
lib/semihosting.c.

On Thu, Sep 15, 2022 at 8:55 PM Sean Anderson <sean.anderson at seco.com> wrote:
>
> Hi Kautuk,
>
> On 9/15/22 8:45 AM, Kautuk Consul wrote:
> > [You don't often get email from kconsul at ventanamicro.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >
> > Semihosting is a mechanism that enables code running on
> > a target to communicate and use the Input/Output
> > facilities on a host computer that is running a debugger.
> > This patchset adds support for semihosting in u-boot
> > for RISCV64 targets.
> >
> > Compilation and test commands for SPL and S-mode configurations
> > =================================================================
> >
> > U-Boot S-mode on QEMU virt
> > ----------------------------
> > // Compilation of S-mode u-boot
> > ARCH=riscv
> > CROSS_COMPILE=riscv64-unknown-linux-gnu-
> > make qemu-riscv64_smode_defconfig
> > make
> > // Run riscv 64-bit u-boot with opensbi on qemu
> > qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\
> > opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\
> > u-boot/u-boot.bin
> >
> > U-Boot SPL on QEMU virt
> > ------------------------
> > // Compilation of u-boot-spl
> > ARCH=riscv
> > CROSS_COMPILE=riscv64-unknown-linux-gnu-
> > make qemu-riscv64_spl_defconfig
> > make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin
> > // Run 64-bit u-boot-spl in qemu
> > qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\
> > u-boot/spl/u-boot-spl.bin -device\
> > loader,file=u-boot/u-boot.itb,addr=0x80200000
> >
> > Kautuk Consul (2):
> >   arch/riscv: add semihosting support for RISC-V
> >   board: qemu-riscv: enable semihosting
> >
> >  arch/riscv/Kconfig                   |  45 ++++++++
> >  arch/riscv/include/asm/semihosting.h |  11 ++
> >  arch/riscv/include/asm/spl.h         |   1 +
> >  arch/riscv/lib/Makefile              |   7 ++
> >  arch/riscv/lib/semihosting.c         | 166 +++++++++++++++++++++++++++
> >  arch/riscv/lib/semihosting_mmode.c   |  77 +++++++++++++
> >  arch/riscv/lib/semihosting_smode.c   |  77 +++++++++++++
>
> I don't think this is the right approach. The semihosting ABI is
> effectively identical on Arm and RISC-V, with the exception of the
> actual trap instruction. I think we should add support for RISC-V by
> moving the semihosting code (and Kconfig options) to e.g. lib/, and
> reduce the arch-specific code to just smh_trap (and any exception
> handlers).
>
> Does that seem reasonable to you?
>
> --Sean
>
> >  configs/qemu-riscv32_defconfig       |   4 +
> >  configs/qemu-riscv32_smode_defconfig |   4 +
> >  configs/qemu-riscv32_spl_defconfig   |   5 +
> >  configs/qemu-riscv64_defconfig       |   4 +
> >  configs/qemu-riscv64_smode_defconfig |   4 +
> >  configs/qemu-riscv64_spl_defconfig   |   5 +
> >  include/configs/qemu-riscv.h         |   2 +
> >  14 files changed, 412 insertions(+)
> >  create mode 100644 arch/riscv/include/asm/semihosting.h
> >  create mode 100644 arch/riscv/lib/semihosting.c
> >  create mode 100644 arch/riscv/lib/semihosting_mmode.c
> >  create mode 100644 arch/riscv/lib/semihosting_smode.c
> >
> > --
> > 2.34.1
> >