[PATCH v2] ARM: imx: Deduplicate i.MX8M SNVS LPGPR unlock

[Peng Fan]

Hi Marek,

On 9/20/2022 3:37 AM, Marek Vasut wrote:
> Pull this LPGPR unlock into common code, since it is used in multiple
> systems already.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> ---
> Cc: Fabio Estevam <festevam at denx.de>
> Cc: Peng Fan <peng.fan at nxp.com>
> Cc: Stefano Babic <sbabic at denx.de>
> Cc: Ye Li <ye.li at nxp.com>
> Cc: uboot-imx <uboot-imx at nxp.com>
> ---
> V2: Reinstate empty board_init() in DM eDM SBC board to fix build error
> ---
>   arch/arm/include/asm/arch-imx8m/imx-regs.h      |  5 +++++
>   arch/arm/mach-imx/imx8m/soc.c                   | 12 ++++++++++++
>   .../imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c  | 17 -----------------
>   .../dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c | 17 -----------------
>   board/menlo/mx8menlo/mx8menlo.c                 | 17 -----------------
>   5 files changed, 17 insertions(+), 51 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
> index ff3b9ddd9f7..29d5baaab8b 100644
> --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
> +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
> @@ -27,6 +27,7 @@
>   #define IOMUXC_GPR_BASE_ADDR	0x30340000
>   #define OCOTP_BASE_ADDR		0x30350000
>   #define ANATOP_BASE_ADDR	0x30360000
> +#define SNVS_BASE_ADDR		0x30370000
>   #define CCM_BASE_ADDR		0x30380000
>   #define SRC_BASE_ADDR		0x30390000
>   #define GPC_BASE_ADDR		0x303A0000
> @@ -113,6 +114,10 @@
>   #define SRC_DDR1_RCR_CORE_RESET_N_MASK	BIT(1)
>   #define SRC_DDR1_RCR_PRESET_N_MASK	BIT(0)
>   
> +#define SNVS_LPSR			0x4c
> +#define SNVS_LPLVDR			0x64
> +#define SNVS_LPPGDR_INIT		0x41736166
> +
>   struct iomuxc_gpr_base_regs {
>   	u32 gpr[47];
>   };
> diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
> index d115b25a5b6..5739546c022 100644
> --- a/arch/arm/mach-imx/imx8m/soc.c
> +++ b/arch/arm/mach-imx/imx8m/soc.c
> @@ -544,6 +544,16 @@ static int imx8m_check_clock(void *ctx, struct event *event)
>   }
>   EVENT_SPY(EVT_DM_POST_INIT, imx8m_check_clock);
>   
> +static void imx8m_setup_snvs(void)
> +{
> +	/* Enable SNVS clock */
> +	clock_enable(CCGR_SNVS, 1);
> +	/* Initialize glitch detect */
> +	writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
> +	/* Clear interrupt status */
> +	writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
> +}


SNVS CCGR default should be enabling clk, that is
hardware default settings.

Why need enable clk here?

Honestly I am not very familar with this IP, except
RTC. what are the settings used for?

Thanks,
Peng.

> +
>   int arch_cpu_init(void)
>   {
>   	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
> @@ -594,6 +604,8 @@ int arch_cpu_init(void)
>   			writel(0x200, &ocotp->ctrl_clr);
>   	}
>   
> +	imx8m_setup_snvs();
> +
>   	return 0;
>   }
>   
> diff --git a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c
> index 6dc4e6a9a2b..dc0883002c8 100644
> --- a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c
> +++ b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c
> @@ -34,22 +34,6 @@ int board_phys_sdram_size(phys_size_t *size)
>   	return 0;
>   }
>   
> -/* IMX8M SNVS registers needed for the bootcount functionality */
> -#define SNVS_BASE_ADDR			0x30370000
> -#define SNVS_LPSR			0x4c
> -#define SNVS_LPLVDR			0x64
> -#define SNVS_LPPGDR_INIT		0x41736166
> -
> -static void setup_snvs(void)
> -{
> -	/* Enable SNVS clock */
> -	clock_enable(CCGR_SNVS, 1);
> -	/* Initialize glitch detect */
> -	writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
> -	/* Clear interrupt status */
> -	writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
> -}
> -
>   static void setup_mac_address(void)
>   {
>   	unsigned char enetaddr[6];
> @@ -99,7 +83,6 @@ static void setup_boot_device(void)
>   
>   int board_init(void)
>   {
> -	setup_snvs();
>   	return 0;
>   }
>   
> diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
> index 6f06daf86f7..9d8e19d994a 100644
> --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
> +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
> @@ -37,22 +37,6 @@ int board_phys_sdram_size(phys_size_t *size)
>   	return 0;
>   }
>   
> -/* IMX8M SNVS registers needed for the bootcount functionality */
> -#define SNVS_BASE_ADDR			0x30370000
> -#define SNVS_LPSR			0x4c
> -#define SNVS_LPLVDR			0x64
> -#define SNVS_LPPGDR_INIT		0x41736166
> -
> -static void setup_snvs(void)
> -{
> -	/* Enable SNVS clock */
> -	clock_enable(CCGR_SNVS, 1);
> -	/* Initialize glitch detect */
> -	writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
> -	/* Clear interrupt status */
> -	writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
> -}
> -
>   static void setup_eqos(void)
>   {
>   	struct iomuxc_gpr_base_regs *gpr =
> @@ -145,7 +129,6 @@ int board_init(void)
>   {
>   	setup_eqos();
>   	setup_fec();
> -	setup_snvs();
>   	return 0;
>   }
>   
> diff --git a/board/menlo/mx8menlo/mx8menlo.c b/board/menlo/mx8menlo/mx8menlo.c
> index 9d3708a3637..61fc4ec85f0 100644
> --- a/board/menlo/mx8menlo/mx8menlo.c
> +++ b/board/menlo/mx8menlo/mx8menlo.c
> @@ -12,24 +12,7 @@
>   #include <asm/mach-imx/iomux-v3.h>
>   #include <spl.h>
>   
> -#define SNVS_BASE_ADDR		0x30370000
> -#define SNVS_LPSR		0x4c
> -#define SNVS_LPLVDR		0x64
> -#define SNVS_LPPGDR_INIT	0x41736166
> -
> -static void setup_snvs(void)
> -{
> -	/* Enable SNVS clock */
> -	clock_enable(CCGR_SNVS, 1);
> -	/* Initialize glitch detect */
> -	writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
> -	/* Clear interrupt status */
> -	writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
> -}
> -
>   void board_early_init(void)
>   {
>   	init_uart_clk(1);
> -
> -	setup_snvs();
>   }