[PATCH v3 5/6] arm: mvebu: Support for 98DX25xx/98DX35xx SoC

[Chris Packham]

On Wed, Sep 21, 2022 at 5:58 PM Stefan Roese <sr at denx.de> wrote:
>
> On 21.09.22 06:59, Chris Packham wrote:
> > Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with
> > an integrated CPU (referred to as the CnM block in Marvell's
> > documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support
> > has been ported from Marvell's SDK which is based on a much older
> > version of U-Boot.
> >
> > Signed-off-by: Chris Packham <judge.packham at gmail.com>
> > ---
> >

<snip>

> > diff --git a/arch/arm/mach-mvebu/alleycat5/soc.c b/arch/arm/mach-mvebu/alleycat5/soc.c
> > new file mode 100644
> > index 0000000000..f388d4ee40
> > --- /dev/null
> > +++ b/arch/arm/mach-mvebu/alleycat5/soc.c

<snip>

> > +int soc_early_init_f(void)
> > +{
> > +#ifdef CONFIG_MVEBU_SAR
> > +/* Sample at reset register init */
> > +     mvebu_sar_init();
> > +#endif
>
> Won't CONFIG_MVEBU_SAR always be enabled? Remove the #ifdef in this
> case.
>
> > +     return 0;
> > +}

Currently it is possible to turn it off. As I've said I think I do
need to look at the whole SAR business and see if it can be done
differently.

One useful thing it does do is tell me about how the hardware has been
strapped. U-Boot itself doesn't care about that specifically as the
separate mv_ddr blob that runs before ATF is the thing that actually
uses the SAR values. But U-
Boot is the first place that can give me some friendly output about
the board and knowing the CPU/DDR clock speed is useful at that level.