[PATCH v2] ARM: imx: Deduplicate i.MX8M SNVS LPGPR unlock

[Peng Fan]

On 9/22/2022 10:44 AM, Marek Vasut wrote:
> On 9/21/22 07:45, Peng Fan wrote:
> 
> Hi,
> 
> [...]
> 
>>> @@ -544,6 +544,16 @@ static int imx8m_check_clock(void *ctx, struct
>>> event *event)
>>>    }
>>>    EVENT_SPY(EVT_DM_POST_INIT, imx8m_check_clock);
>>> +static void imx8m_setup_snvs(void)
>>> +{
>>> +    /* Enable SNVS clock */
>>> +    clock_enable(CCGR_SNVS, 1);
>>> +    /* Initialize glitch detect */
>>> +    writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
>>> +    /* Clear interrupt status */
>>> +    writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
>>> +}
>>
>>
>> SNVS CCGR default should be enabling clk, that is
>> hardware default settings.
>>
>> Why need enable clk here?
> 
> To enable clock to the IP, they are not always enabled on boot which
> leads to hang.

Not sure where the clk would be disabled. Kernel should
mark this clk as critical clk. U-Boot would not disable the clk.

> 
>> Honestly I am not very familar with this IP, except
>> RTC. what are the settings used for?
> 
> To store bootcounter e.g. for redundant A/B boot setup.

Got it.

Thanks,
Peng.

> 
> [...]