[PATCH 3/3] net: phy: Synchronize PHY interface modes with Linux
Ramon Fried
rfried.dev at gmail.com
Sat Apr 1 20:48:55 CEST 2023
On Sun, Mar 19, 2023 at 7:07 PM Marek Vasut
<marek.vasut+renesas at mailbox.org> wrote:
>
> Synchronize PHY interface modes with Linux next 6.2.y commit:
> 0194b64578e90 ("net: phy: improve phy_read_poll_timeout")
>
> Retain LX2160A/LX2162A PHY modes as those are not yet supported
> by the Linux kernel, but isolate those with ifdeffery.
>
> Isolate NCSI which are also not supported by Linux kernel. Note
> that the ifdeffery cannot be avoided with IS_ENABLED() here due
> to compilation of the entire conditional, which would fail in
> case NCSI symbols are not available.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas at mailbox.org>
> ---
> Cc: "Ariel D'Alessandro" <ariel.dalessandro at collabora.com>
> Cc: "Marek Behún" <kabel at kernel.org>
> Cc: Joe Hershberger <joe.hershberger at ni.com>
> Cc: Marek Vasut <marek.vasut+renesas at mailbox.org>
> Cc: Ramon Fried <rfried.dev at gmail.com>
> Cc: Stefan Roese <sr at denx.de>
> Cc: Tim Harvey <tharvey at gateworks.com>
> Cc: Vladimir Oltean <vladimir.oltean at nxp.com>
> ---
> drivers/net/phy/phy.c | 4 +++
> include/phy_interface.h | 68 +++++++++++++++++++++++++++++------------
> 2 files changed, 53 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> index 9b0e497f223..f720d0a7920 100644
> --- a/drivers/net/phy/phy.c
> +++ b/drivers/net/phy/phy.c
> @@ -1160,7 +1160,11 @@ int phy_clear_bits_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val
>
> bool phy_interface_is_ncsi(void)
> {
> +#ifdef CONFIG_PHY_NCSI
> struct eth_pdata *pdata = dev_get_plat(eth_get_dev());
>
> return pdata->phy_interface == PHY_INTERFACE_MODE_NCSI;
> +#else
> + return 0;
> +#endif
> }
> diff --git a/include/phy_interface.h b/include/phy_interface.h
> index 52af7e612b6..31be3228c7c 100644
> --- a/include/phy_interface.h
> +++ b/include/phy_interface.h
> @@ -14,65 +14,95 @@
>
> typedef enum {
> PHY_INTERFACE_MODE_NA, /* don't touch */
> + PHY_INTERFACE_MODE_INTERNAL,
> PHY_INTERFACE_MODE_MII,
> PHY_INTERFACE_MODE_GMII,
> PHY_INTERFACE_MODE_SGMII,
> - PHY_INTERFACE_MODE_SGMII_2500,
> - PHY_INTERFACE_MODE_QSGMII,
> PHY_INTERFACE_MODE_TBI,
> + PHY_INTERFACE_MODE_REVMII,
> PHY_INTERFACE_MODE_RMII,
> + PHY_INTERFACE_MODE_REVRMII,
> PHY_INTERFACE_MODE_RGMII,
> PHY_INTERFACE_MODE_RGMII_ID,
> PHY_INTERFACE_MODE_RGMII_RXID,
> PHY_INTERFACE_MODE_RGMII_TXID,
> PHY_INTERFACE_MODE_RTBI,
> + PHY_INTERFACE_MODE_SMII,
> + PHY_INTERFACE_MODE_XGMII,
> + PHY_INTERFACE_MODE_XLGMII,
> + PHY_INTERFACE_MODE_MOCA,
> + PHY_INTERFACE_MODE_QSGMII,
> + PHY_INTERFACE_MODE_TRGMII,
> + PHY_INTERFACE_MODE_100BASEX,
> PHY_INTERFACE_MODE_1000BASEX,
> PHY_INTERFACE_MODE_2500BASEX,
> - PHY_INTERFACE_MODE_XGMII,
> - PHY_INTERFACE_MODE_XAUI,
> - PHY_INTERFACE_MODE_RXAUI,
> PHY_INTERFACE_MODE_5GBASER,
> - PHY_INTERFACE_MODE_SFI,
> - PHY_INTERFACE_MODE_INTERNAL,
> + PHY_INTERFACE_MODE_RXAUI,
> + PHY_INTERFACE_MODE_XAUI,
> + /* 10GBASE-R, XFI, SFI - single lane 10G Serdes */
> + PHY_INTERFACE_MODE_10GBASER,
> + PHY_INTERFACE_MODE_25GBASER,
> + PHY_INTERFACE_MODE_USXGMII,
> + /* 10GBASE-KR - with Clause 73 AN */
> + PHY_INTERFACE_MODE_10GKR,
> + PHY_INTERFACE_MODE_QUSGMII,
> + PHY_INTERFACE_MODE_1000BASEKX,
> +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
> + /* LX2160A SERDES modes */
> PHY_INTERFACE_MODE_25G_AUI,
> PHY_INTERFACE_MODE_XLAUI,
> PHY_INTERFACE_MODE_CAUI2,
> PHY_INTERFACE_MODE_CAUI4,
> +#endif
> +#if defined(CONFIG_PHY_NCSI)
> PHY_INTERFACE_MODE_NCSI,
> - PHY_INTERFACE_MODE_10GBASER,
> - PHY_INTERFACE_MODE_USXGMII,
> +#endif
> PHY_INTERFACE_MODE_MAX,
> } phy_interface_t;
>
> static const char * const phy_interface_strings[] = {
> - [PHY_INTERFACE_MODE_NA] = "",
> + [PHY_INTERFACE_MODE_NA] = "",
> + [PHY_INTERFACE_MODE_INTERNAL] = "internal",
> [PHY_INTERFACE_MODE_MII] = "mii",
> [PHY_INTERFACE_MODE_GMII] = "gmii",
> [PHY_INTERFACE_MODE_SGMII] = "sgmii",
> - [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
> - [PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
> [PHY_INTERFACE_MODE_TBI] = "tbi",
> + [PHY_INTERFACE_MODE_REVMII] = "rev-mii",
> [PHY_INTERFACE_MODE_RMII] = "rmii",
> + [PHY_INTERFACE_MODE_REVRMII] = "rev-rmii",
> [PHY_INTERFACE_MODE_RGMII] = "rgmii",
> [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
> [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
> [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
> [PHY_INTERFACE_MODE_RTBI] = "rtbi",
> + [PHY_INTERFACE_MODE_SMII] = "smii",
> + [PHY_INTERFACE_MODE_XGMII] = "xgmii",
> + [PHY_INTERFACE_MODE_XLGMII] = "xlgmii",
> + [PHY_INTERFACE_MODE_MOCA] = "moca",
> + [PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
> + [PHY_INTERFACE_MODE_TRGMII] = "trgmii",
> [PHY_INTERFACE_MODE_1000BASEX] = "1000base-x",
> + [PHY_INTERFACE_MODE_1000BASEKX] = "1000base-kx",
> [PHY_INTERFACE_MODE_2500BASEX] = "2500base-x",
> - [PHY_INTERFACE_MODE_XGMII] = "xgmii",
> - [PHY_INTERFACE_MODE_XAUI] = "xaui",
> - [PHY_INTERFACE_MODE_RXAUI] = "rxaui",
> [PHY_INTERFACE_MODE_5GBASER] = "5gbase-r",
> - [PHY_INTERFACE_MODE_SFI] = "sfi",
> - [PHY_INTERFACE_MODE_INTERNAL] = "internal",
> + [PHY_INTERFACE_MODE_RXAUI] = "rxaui",
> + [PHY_INTERFACE_MODE_XAUI] = "xaui",
> + [PHY_INTERFACE_MODE_10GBASER] = "10gbase-r",
> + [PHY_INTERFACE_MODE_25GBASER] = "25gbase-r",
> + [PHY_INTERFACE_MODE_USXGMII] = "usxgmii",
> + [PHY_INTERFACE_MODE_10GKR] = "10gbase-kr",
> + [PHY_INTERFACE_MODE_100BASEX] = "100base-x",
> + [PHY_INTERFACE_MODE_QUSGMII] = "qusgmii",
> +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
> + /* LX2160A SERDES modes */
> [PHY_INTERFACE_MODE_25G_AUI] = "25g-aui",
> [PHY_INTERFACE_MODE_XLAUI] = "xlaui4",
> [PHY_INTERFACE_MODE_CAUI2] = "caui2",
> [PHY_INTERFACE_MODE_CAUI4] = "caui4",
> +#endif
> +#if defined(CONFIG_PHY_NCSI)
> [PHY_INTERFACE_MODE_NCSI] = "NC-SI",
> - [PHY_INTERFACE_MODE_10GBASER] = "10gbase-r",
> - [PHY_INTERFACE_MODE_USXGMII] = "usxgmii",
> +#endif
> };
>
> /* Backplane modes:
> --
> 2.39.2
>
Reviewed-by: Ramon Fried <rfried.dev at gmail.com>
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