[PATCH 4/5] net: phy: Add MDIO PCS 2.5G and 5G speed macros from Linux

[Ramon Fried]

On Sun, Mar 19, 2023 at 7:08 PM Marek Vasut
<marek.vasut+renesas at mailbox.org> wrote:
>
> Add MDIO PCS 2.5G and 5G speed macros from Linux 5.1.y as of commit
> 7fd8afa8933a0 ("net: phy: Add generic support for 2.5GBaseT and 5GBaseT")
> This is used by the upcoming Marvell 10G PHY driver.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas at mailbox.org>
> ---
> Cc: "Ariel D'Alessandro" <ariel.dalessandro at collabora.com>
> Cc: "Marek Behún" <kabel at kernel.org>
> Cc: Joe Hershberger <joe.hershberger at ni.com>
> Cc: Marek Vasut <marek.vasut+renesas at mailbox.org>
> Cc: Michael Trimarchi <michael at amarulasolutions.com>
> Cc: Nate Drude <nate.d at variscite.com>
> Cc: Ramon Fried <rfried.dev at gmail.com>
> Cc: Simon Glass <sjg at chromium.org>
> Cc: Stefan Roese <sr at denx.de>
> Cc: Tim Harvey <tharvey at gateworks.com>
> Cc: Vladimir Oltean <vladimir.oltean at nxp.com>
> ---
>  include/linux/mdio.h | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
>
> diff --git a/include/linux/mdio.h b/include/linux/mdio.h
> index 6e821d906fb..b7c845155e4 100644
> --- a/include/linux/mdio.h
> +++ b/include/linux/mdio.h
> @@ -44,6 +44,7 @@
>  #define MDIO_AN_ADVERTISE      16      /* AN advertising (base page) */
>  #define MDIO_AN_LPA            19      /* AN LP abilities (base page) */
>  #define MDIO_PCS_EEE_ABLE      20      /* EEE Capability register */
> +#define MDIO_PMA_NG_EXTABLE    21      /* 2.5G/5G PMA/PMD extended ability */
>  #define MDIO_PCS_EEE_WK_ERR    22      /* EEE wake error counter */
>  #define MDIO_PHYXS_LNSTAT      24      /* PHY XGXS lane state */
>  #define MDIO_AN_EEE_ADV                60      /* EEE advertisement */
> @@ -91,6 +92,10 @@
>  #define MDIO_CTRL1_SPEED10G            (MDIO_CTRL1_SPEEDSELEXT | 0x00)
>  /* 10PASS-TS/2BASE-TL */
>  #define MDIO_CTRL1_SPEED10P2B          (MDIO_CTRL1_SPEEDSELEXT | 0x04)
> +/* 2.5 Gb/s */
> +#define MDIO_CTRL1_SPEED2_5G           (MDIO_CTRL1_SPEEDSELEXT | 0x18)
> +/* 5 Gb/s */
> +#define MDIO_CTRL1_SPEED5G             (MDIO_CTRL1_SPEEDSELEXT | 0x1c)
>
>  /* Status register 1. */
>  #define MDIO_STAT1_LPOWERABLE          0x0002  /* Low-power ability */
> @@ -111,6 +116,8 @@
>  #define MDIO_PMA_SPEED_100             0x0020  /* 100M capable */
>  #define MDIO_PMA_SPEED_10              0x0040  /* 10M capable */
>  #define MDIO_PCS_SPEED_10P2B           0x0002  /* 10PASS-TS/2BASE-TL capable */
> +#define MDIO_PCS_SPEED_2_5G            0x0040  /* 2.5G capable */
> +#define MDIO_PCS_SPEED_5G              0x0080  /* 5G capable */
>
>  /* Device present registers. */
>  #define MDIO_DEVS_PRESENT(devad)       (1 << (devad))
> @@ -150,6 +157,8 @@
>  #define MDIO_PMA_CTRL2_1000BKX         0x000d  /* 1000BASE-KX type */
>  #define MDIO_PMA_CTRL2_100BTX          0x000e  /* 100BASE-TX type */
>  #define MDIO_PMA_CTRL2_10BT            0x000f  /* 10BASE-T type */
> +#define MDIO_PMA_CTRL2_2_5GBT          0x0030  /* 2.5GBaseT type */
> +#define MDIO_PMA_CTRL2_5GBT            0x0031  /* 5GBaseT type */
>  #define MDIO_PCS_CTRL2_TYPE            0x0003  /* PCS type selection */
>  #define MDIO_PCS_CTRL2_10GBR           0x0000  /* 10GBASE-R type */
>  #define MDIO_PCS_CTRL2_10GBX           0x0001  /* 10GBASE-X type */
> @@ -203,6 +212,7 @@
>  #define MDIO_PMA_EXTABLE_1000BKX       0x0040  /* 1000BASE-KX ability */
>  #define MDIO_PMA_EXTABLE_100BTX                0x0080  /* 100BASE-TX ability */
>  #define MDIO_PMA_EXTABLE_10BT          0x0100  /* 10BASE-T ability */
> +#define MDIO_PMA_EXTABLE_NBT           0x4000  /* 2.5/5GBASE-T ability */
>
>  /* PHY XGXS lane state register. */
>  #define MDIO_PHYXS_LNSTAT_SYNC0                0x0001
> @@ -239,9 +249,13 @@
>  #define MDIO_PCS_10GBRT_STAT2_BER      0x3f00
>
>  /* AN 10GBASE-T control register. */
> +#define MDIO_AN_10GBT_CTRL_ADV2_5G     0x0080  /* Advertise 2.5GBASE-T */
> +#define MDIO_AN_10GBT_CTRL_ADV5G       0x0100  /* Advertise 5GBASE-T */
>  #define MDIO_AN_10GBT_CTRL_ADV10G      0x1000  /* Advertise 10GBASE-T */
>
>  /* AN 10GBASE-T status register. */
> +#define MDIO_AN_10GBT_STAT_LP2_5G      0x0020  /* LP is 2.5GBT capable */
> +#define MDIO_AN_10GBT_STAT_LP5G                0x0040  /* LP is 5GBT capable */
>  #define MDIO_AN_10GBT_STAT_LPTRR       0x0200  /* LP training reset req. */
>  #define MDIO_AN_10GBT_STAT_LPLTABLE    0x0400  /* LP loop timing ability */
>  #define MDIO_AN_10GBT_STAT_LP10G       0x0800  /* LP is 10GBT capable */
> @@ -270,6 +284,10 @@
>  #define MDIO_EEE_10GKX4                0x0020  /* 10G KX4 EEE cap */
>  #define MDIO_EEE_10GKR         0x0040  /* 10G KR EEE cap */
>
> +/* 2.5G/5G Extended abilities register. */
> +#define MDIO_PMA_NG_EXTABLE_2_5GBT     0x0001  /* 2.5GBASET ability */
> +#define MDIO_PMA_NG_EXTABLE_5GBT       0x0002  /* 5GBASET ability */
> +
>  /* LASI RX_ALARM control/status registers. */
>  #define MDIO_PMA_LASI_RX_PHYXSLFLT     0x0001  /* PHY XS RX local fault */
>  #define MDIO_PMA_LASI_RX_PCSLFLT       0x0008  /* PCS RX local fault */
> --
> 2.39.2
>
Reviewed-by: Ramon Fried <rfried.dev at gmail.com>