[PATCH v3 1/3] ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB 2.0 host

Eugen Hristev eugen.hristev at collabora.com
Mon Apr 3 13:28:33 CEST 2023


On 4/2/23 14:00, Jonas Karlman wrote:
> Hi Eugen,
> 
> On 2023-03-31 11:40, Eugen Hristev wrote:
>> Add USB 2.0 host nodes and PHYs.
>>
>> Co-developed-by: William Wu <william.wu at rock-chips.com>
>> Signed-off-by: William Wu <william.wu at rock-chips.com>
>> Signed-off-by: Eugen Hristev <eugen.hristev at collabora.com>
>> ---
>> Changes in v2,v3:
>> - none
>>
>>   arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 169 ++++++++++++++++++++++++
>>   1 file changed, 169 insertions(+)
>>
>> diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
>> index 2386edf90deb..e1d240baf35d 100644
>> --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
>> +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
>> @@ -4,6 +4,9 @@
>>    */
>>   
>>   #include "rk3588-u-boot.dtsi"
>> +#include <dt-bindings/pinctrl/rockchip.h>
>> +#include <dt-bindings/input/input.h>
>> +#include <dt-bindings/gpio/gpio.h>
>>   
>>   / {
>>   	aliases {
>> @@ -13,6 +16,105 @@
>>   	chosen {
>>   		u-boot,spl-boot-order = &sdmmc;
>>   	};
>> +
>> +	vcc5v0_host: vcc5v0-host-regulator {
>> +		u-boot,dm-pre-reloc;
>> +		compatible = "regulator-fixed";
>> +		regulator-name = "vcc5v0_host";
>> +		regulator-min-microvolt = <5000000>;
>> +		regulator-max-microvolt = <5000000>;
>> +		enable-active-high;
>> +		gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
>> +		pinctrl-names = "default";
>> +		pinctrl-0 = <&vcc5v0_host_en>;
>> +		vin-supply = <&vcc5v0_sys>;
>> +	};
>> +
>> +	usb_host0_ehci: usb at fc800000 {
>> +		compatible = "generic-ehci";
>> +		reg = <0x0 0xfc800000 0x0 0x40000>;
>> +		interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
>> +		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
>> +		clock-names = "usbhost", "arbiter";
>> +		power-domains = <&power RK3588_PD_USB>;
>> +		status = "disabled";
>> +	};
>> +
>> +	usb_host0_ohci: usb at fc840000 {
>> +		compatible = "generic-ohci";
>> +		reg = <0x0 0xfc840000 0x0 0x40000>;
>> +		interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
>> +		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
>> +		clock-names = "usbhost", "arbiter";
>> +		power-domains = <&power RK3588_PD_USB>;
>> +		status = "disabled";
>> +	};
>> +
>> +	usb_host1_ehci: usb at fc880000 {
>> +		compatible = "generic-ehci";
>> +		reg = <0x0 0xfc880000 0x0 0x40000>;
>> +		interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
>> +		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
>> +		clock-names = "usbhost", "arbiter";
>> +		power-domains = <&power RK3588_PD_USB>;
>> +		status = "disabled";
>> +	};
>> +
>> +	usb_host1_ohci: usb at fc8c0000 {
>> +		compatible = "generic-ohci";
>> +		reg = <0x0 0xfc8c0000 0x0 0x40000>;
>> +		interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
>> +		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
>> +		clock-names = "usbhost", "arbiter";
>> +		power-domains = <&power RK3588_PD_USB>;
>> +		status = "disabled";
>> +	};
>> +
>> +	usb2phy2_grf: syscon at fd5d8000 {
>> +		compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
>> +			     "simple-mfd";
>> +		reg = <0x0 0xfd5d8000 0x0 0x4000>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +
>> +		u2phy2: usb2-phy at 8000 {
>> +			compatible = "rockchip,rk3588-usb2phy";
>> +			reg = <0x8000 0x10>;
>> +			interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
>> +			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
>> +			clock-names = "phyclk";
>> +			#clock-cells = <0>;
>> +			status = "disabled";
>> +
>> +			u2phy2_host: host-port {
>> +				#phy-cells = <0>;
>> +				status = "disabled";
>> +			};
>> +		};
>> +	};
>> +
>> +	usb2phy3_grf: syscon at fd5dc000 {
>> +		compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
>> +			     "simple-mfd";
>> +		reg = <0x0 0xfd5dc000 0x0 0x4000>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +
>> +		u2phy3: usb2-phy at c000 {
>> +			compatible = "rockchip,rk3588-usb2phy";
>> +			reg = <0xc000 0x10>;
>> +			interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
>> +			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
>> +			clock-names = "phyclk";
>> +			#clock-cells = <0>;
>> +			status = "disabled";
>> +
>> +			u2phy3_host: host-port {
>> +				#phy-cells = <0>;
>> +				status = "disabled";
>> +			};
>> +		};
>> +	};
> 
> Most of these nodes could be added to the soc u-boot dtsi and not the
> board specific file. Also wondering if some of the reset and clock
> related properties below are board specific or soc specific and can go
> into the above soc nodes directly.

That is right, but , it would spread all the -u-boot.dtsi nodes into a 
lot of files. So I kept them here to have them all in one place.
I can move them if you think it's better.

> 
> Are there any patches in the works to add these nodes to linux dt?
 From what I know, yes, the patches are in the works, but I cannot say 
for sure when they will be sent/accepted

> 
> Regards,
> Jonas
> 
>>   };
>>   
>>   &sdmmc {
>> @@ -20,3 +122,70 @@
>>   	u-boot,dm-spl;
>>   	status = "okay";
>>   };
>> +
>> +&pinctrl {
>> +	usb {
>> +		vcc5v0_host_en: vcc5v0-host-en {
>> +			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
>> +		};
>> +	};
>> +};
>> +
>> +&usb_host0_ehci {
>> +	companion = <&usb_host0_ohci>;
>> +	phys = <&u2phy2_host>;
>> +	phy-names = "usb2-phy";
>> +	status = "okay";
>> +};
>> +
>> +&usb_host0_ohci {
>> +	phys = <&u2phy2_host>;
>> +	phy-names = "usb2-phy";
>> +	status = "okay";
>> +};
>> +
>> +&usb2phy2_grf {
>> +	status = "okay";
>> +};
>> +
>> +&u2phy2 {
>> +	resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
>> +	reset-names = "phy", "apb";
>> +	clock-output-names = "usb480m_phy2";
>> +	status = "okay";
>> +};
>> +
>> +&u2phy2_host {
>> +	phy-supply = <&vcc5v0_host>;
>> +	status = "okay";
>> +};
>> +
>> +&usb_host1_ehci {
>> +	companion = <&usb_host1_ohci>;
>> +	phys = <&u2phy3_host>;
>> +	phy-names = "usb2-phy";
>> +	status = "okay";
>> +};
>> +
>> +&usb_host1_ohci {
>> +	phys = <&u2phy3_host>;
>> +	phy-names = "usb2-phy";
>> +	status = "okay";
>> +};
>> +
>> +&usb2phy3_grf {
>> +	status = "okay";
>> +};
>> +
>> +&u2phy3 {
>> +	resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
>> +	reset-names = "phy", "apb";
>> +	clock-output-names = "usb480m_phy3";
>> +	status = "okay";
>> +};
>> +
>> +&u2phy3_host {
>> +	phy-supply = <&vcc5v0_host>;
>> +	status = "okay";
>> +};
>> +
> 



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