[PATCH 1/2] clk: rockchip: rk3588: add hardcoded assigned clocks values

[Kever Yang]

On 2023/4/13 19:36, Eugen Hristev wrote:
> The CRU is being probed with a default set of assigned clocks, which
> are not implemented in the driver at all.
> Hence, when clk_set_defaults is called, it fails with ENOENT.
> This would not be a problem, as the CRU still handles all the required
> clocks, and the assigned clocks are default configs which are preprogrammed
> or not required for Uboot operations.
> However, the rockchip reset driver is being bound by the same DT node
> as CRU, as the reset driver has no DT node.
> But, when probing the reset node, it will call again the clk_set_defaults
> for the CRU node, and failing because of missing those specific clocks
> in the rk3588 clock driver.
> To avoid this, simply implement a basic set/get that will just return
> success and the default corresponding rate for the required assigned clocks.
> As those clocks were not supported in Uboot, not required for Uboot
> operations, there is no need to do any different kind of initialization.
>
> Signed-off-by: Eugen Hristev <eugen.hristev at collabora.com>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever

> ---
>   drivers/clk/rockchip/clk_rk3588.c | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
> index 41e31b61a55b..c93c9c304d40 100644
> --- a/drivers/clk/rockchip/clk_rk3588.c
> +++ b/drivers/clk/rockchip/clk_rk3588.c
> @@ -1556,6 +1556,21 @@ static ulong rk3588_clk_get_rate(struct clk *clk)
>   	case TCLK_WDT0:
>   		rate = OSC_HZ;
>   		break;
> +	case PCLK_PMU0_ROOT:
> +		rate = 100000000;
> +		break;
> +	case HCLK_PMU_CM0_ROOT:
> +		rate = 200000000;
> +		break;
> +	case ACLK_BUS_ROOT:
> +		rate = 375000000;
> +		break;
> +	case CLK_150M_SRC:
> +		rate = 150000000;
> +		break;
> +	case CLK_GPU:
> +		rate = 200000000;
> +		break;
>   #ifndef CONFIG_SPL_BUILD
>   	case CLK_AUX16M_0:
>   	case CLK_AUX16M_1:
> @@ -1705,6 +1720,13 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate)
>   	case TCLK_WDT0:
>   		ret = OSC_HZ;
>   		break;
> +	case PCLK_PMU0_ROOT:
> +	case CLK_GPU:
> +	case HCLK_PMU_CM0_ROOT:
> +	case ACLK_BUS_ROOT:
> +	case CLK_150M_SRC:
> +		ret = 0;
> +		break;
>   #ifndef CONFIG_SPL_BUILD
>   	case CLK_AUX16M_0:
>   	case CLK_AUX16M_1: