[PATCH v4 08/10] board: schneider: add RZN1 board support

[Marek Vasut]

On 3/8/23 21:26, Ralph Siemsen wrote:

[...]

> diff --git a/board/schneider/rzn1-snarc/ddr_timing.c b/board/schneider/rzn1-snarc/ddr_timing.c
> new file mode 100644
> index 0000000000..8bc3fe7be4
> --- /dev/null
> +++ b/board/schneider/rzn1-snarc/ddr_timing.c
> @@ -0,0 +1,140 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <asm/types.h>
> +
> +#include "jedec_ddr3_2g_x16_1333h_500_cl8.h"
> +
> +u32 ddr_00_87_async[] = {

Should this be 'static u32...' ?

> +	DENALI_CTL_00_DATA,
> +	DENALI_CTL_01_DATA,
> +	DENALI_CTL_02_DATA,
> +	DENALI_CTL_03_DATA,
> +	DENALI_CTL_04_DATA,
> +	DENALI_CTL_05_DATA,
> +	DENALI_CTL_06_DATA,
> +	DENALI_CTL_07_DATA,
> +	DENALI_CTL_08_DATA,
> +	DENALI_CTL_09_DATA,

[...]

> diff --git a/board/schneider/rzn1-snarc/jedec_ddr3_2g_x16_1333h_500_cl8.h b/board/schneider/rzn1-snarc/jedec_ddr3_2g_x16_1333h_500_cl8.h
> new file mode 100644
> index 0000000000..5c55518bc1
> --- /dev/null
> +++ b/board/schneider/rzn1-snarc/jedec_ddr3_2g_x16_1333h_500_cl8.h
> @@ -0,0 +1,399 @@
> +
> +/* ****************************************************************
> + *        CADENCE                    Copyright (c) 2001-2011      *
> + *                                   Cadence Design Systems, Inc. *
> + *                                   All rights reserved.         *
> + *                                                                *
> + ******************************************************************
> + *  The values calculated from this script are meant to be        *
> + *  representative programmings.   The values may not reflect the *
> + *  actual required programming for production use.   Please      *
> + *  closely review all programmed values for technical accuracy   *
> + *  before use in production parts.                               *
> + ******************************************************************
> + *
> + *   Module:         regconfig.h
> + *   Documentation:  Register programming header file
> + *
> + ******************************************************************
> + ******************************************************************
> + * WARNING:  This file was automatically generated.  Manual
> + * editing may result in undetermined behavior.
> + ******************************************************************
> + ******************************************************************/
> +
> +#define               DENALI_CTL_00_DATA 0x00000600

You might want to run checkpatch --f --fix --fix-inplace on this to fix 
formatting , esp. use one space after #define and tab after the macro 
name. Note that diff -wdb will let you diff updates to this file while 
ignoring space changes.

> +#define               DENALI_CTL_01_DATA 0x00000000
> +#define               DENALI_CTL_02_DATA 0x00000000
> +#define               DENALI_CTL_03_DATA 0x00000000
> +#define               DENALI_CTL_04_DATA 0x00000000

[...]

> +++ b/board/schneider/rzn1-snarc/rzn1.c
> @@ -0,0 +1,39 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <asm/global_data.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int board_init(void)
> +{
> +	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
> +
> +	return 0;
> +}
> +
> +int dram_init(void)
> +{
> +	struct udevice *dev;
> +	int err;
> +
> +	/* This will end up calling cadence_ddr_probe() */
> +	err = uclass_get_device(UCLASS_RAM, 0, &dev);
> +	if (err) {
> +		debug("DRAM init failed: %d\n", err);
> +		return err;
> +	}
> +
> +	if (fdtdec_setup_mem_size_base() != 0)
> +		return -EINVAL;
> +
> +	return 0;
> +}
> +
> +int dram_init_banksize(void)
> +{
> +	fdtdec_setup_memory_banksize();
> +
> +	return 0;
> +}

I wonder how much of this should really be in arch/... since this is 
common to all machines with RZN1 . Maybe move it there instead ?

[...]