[PATCH u-boot 2/3] pci: fsl: Do not access PCI BAR0 register of PCIe Root Port

[Heiko Schocher]

Hello Plai,

On 20.04.23 21:44, Pali Rohár wrote:
> Freescale PCIe Root Port has PEXCSRBAR register at position of PCI BAR0.
> PCIe Root Port does not have any PCIe memory, so returns zero when trying
> to read from PCIe Root Port BAR0 and ignore any writes.
> 
> Signed-off-by: Pali Rohár <pali at kernel.org>
> ---
>  drivers/pci/pcie_fsl.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)

Reviewed-by: Heiko Schocher <hs at denx.de>

Thanks!

bye,
Heiko
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